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cl-pd6833 advance data sheet june 1998 version 0.3 pci-to-cardbus host adapter pci bus pc card socket 1 pc card socket 2 cl-pd6833 .................................. .................................. 16 (r2) or 32 (cardbus) pc card .................................. .................................. 16 (r2) or 32 (cardbus) pc card overview features n pin-compatible with the cl-pd6832 n pc 98 v1.0 and pc 97 compliant n supports the pci bus power management interface for pci to cardbus bridges (pcmcia equivalent of acpi) including pme# support n high-performance support for 133-mbyte-per- second transfers n zv (zoomed video) port support for multimedia applications using bypass mode n programmable interrupt protocol: external hardware, pci/way, pci, or pc/pci interrupt signalling modes n up to four multiplexed general-purpose i/o pins n seven fully programmable memory or i/o windows per socket n programmable per-socket activity indicators n bus master capability n pci 2.1, pci 2.2 draft, pc card standard (march 1997), exca ?, and jeida 4.2 compliant n cl-pd672x register set compatible n mixed-voltage support n support for 5-v and 3.3-v pc cards the cl-pd6833 easily interfaces with the 8- and 16-bit r2 pc cards and the 32-bit cardbus pc cards. it is the third device to be developed in cirrus logics family of cardbus controllers. the cl-pd6833 gives system designers of portable, notebook, and handheld computers the most integrated solution for their needs. providing high performance, low-power consumption, and a highly compatible and ?exible interface, the cl-pd6833 enables easy functionality for pc card and cardbus applications such as lans, modems, and multimedia applications. the cl-pd6833 is a single-chip cardbus controller capable of controlling two independent pc card and/or cardbus sockets. featuring enhanced bus traf?c management and cycle pipelining technology, the cl-pd6833 supports transactions at the pci speci?cation limit of 133 mbytes per second. this signi?cantly improves the performance over previous cirrus logic controllers. (cont.) system block diagram
cl-pd6833 pci-to-cardbus host adapter overview (cont.) the cl-pd6833 is compliant with the latest pc 97 and pc 98 design guidelines. the cl-pd6833 is also compliant with pci 2.1, pci 2.2 draft, pc card standard (march 1997), exca ? , and jeida 4.2 standards. like the cl-pd6834, the register set of the cl-pd6833 is a superset of the intel a 365-sl, the cl-pd672x, and the cl-pd6832 register sets; this ensures full compatibility with existing card and socket services software, thus maximizing pc software compatibility. the cl-pd6833 is compliant with the pci bus power management interface for pci to cardbus bridges , which is the pcmcia industrys document for acpi compatibility. the device is also compliant with the pc card controller device class speci?cation. the cl-pd6833 uses state-of-the-art clock control to satisfy industry power consumption targets, thereby assuring minimum power consumption during the various operational and suspend states. the device also offers a hardware suspend mode, which is a method of powering down the host controller to the minimum power consumption levels in addition to acpi-compatible power management features. the acpi-compatible power management features of the cl-pd6833 plus its state-of-the-art clock management and hardware suspend modes ensure that the system designer is provided with all the power management control needed to implement an energy- ef?cient, mixed-voltage cardbus controller. zoomed video support had become an important con- sideration for system designers since 1996. the cl-pd6833 can be programmed to tristate its pc card interface so that graphics and audio signals from a zoomed videoCcapable pc card can be sent to the respective graphics and audio controller zoomed video ports. this solution is practical for multimedia applica- tions such as dvd, full-motion video, and video confer- encing. the cl-pd6833 provides ?exibility in non-pc compatible applications by allowing easy translation of pci bus memory cycles to pc card 16 i/o cycles for processors with memory cycles only. in addition, the cl-pd6833 has up to four multiplexed gpio (general- purpose i/o) pins to interface with external devices that the system designer may wish to implement. notes: 1) dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) the drawing above does not re?ect exact package pin count. 3) before beginning any new design with this device, please contact cirrus logic for the latest package information. pin 1 indicator 25.50 (1.004) ref 30.35 (1.195) 30.85 (1.215) 0.13 (0.005) 0.28 (0.011) 27.90 (1.098) 28.10 (1.106) 25.50 (1.004) ref 0.50 (0.0197) bsc 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 3.17 (0.125) 3.67 (0.144) 0 min 7 max 0.09 (0.004) 0.23 (0.009) 4.07 0.40 (0.016) 0.75 (0.030) 0.25 1.30 (0.051) ref pin 1 pin 208 (0.160) max (0.010) min cl-pd6833 208-pin mqfp pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 0.45 (0.018) 0.75 (0.030) 1.00 (0.039) bsc pin 1 pin 208 cl-pd6833 208-pin lqfp 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006) package outline drawings
june 1998 3 advance data book v0.3 table of contents cl-pd6833 pci-to-cardbus host adapter table of contents 1. conventions.................................................................................................................. .....7 2. pin information .............................................................................................................. ...9 2.1 pin diagrams................................................................................................................ ........................10 2.2 pin description conventions ................................................................................................. ...............12 2.3 pin descriptions ............................................................................................................ .......................13 3. introduction to the cl-pd6833..................................................................................25 3.1 system architecture ......................................................................................................... ....................25 3.1.1 pc card basics............................................................................................................ ...........25 3.1.2 cl-pd6833 r2 windowing capabilities..................................................................................26 3.1.3 zoomed video port ......................................................................................................... ........29 3.1.4 interrupts ................................................................................................................ .................30 3.1.5 pci/way dma ............................................................................................................... ..........34 3.1.6 power management .......................................................................................................... ......34 3.1.7 socket power management features .....................................................................................35 3.1.8 bus sizing ................................................................................................................ ...............37 3.1.9 programmable pc card timing ..............................................................................................3 7 3.1.10 ata mode operation ....................................................................................................... ........37 3.1.11 pc card sensing .......................................................................................................... ..........37 3.2 upgrading from the cl-pd6832 to the cl-pd6833.............................................................................38 3.2.1 added registers........................................................................................................... ...........39 3.3 host access to registers .................................................................................................... .................42 3.4 power-on setup.............................................................................................................. .....................44 4. register description conventions.......................................................................45 5. pci configuration registers....................................................................................47 5.1 vendor id and device id..................................................................................................... .................48 5.2 command and status .......................................................................................................... ................49 5.3 revision id and class code .................................................................................................. ..............52 5.4 cache line size, latency timer, header type, and bist ...................................................................53 5.5 memory base address......................................................................................................... ................54 5.6 cardbus status .............................................................................................................. ......................55 5.7 pci bus number, cardbus number, subordinate bus number, and cardbus latency timer ............57 5.8 memory base 0C1............................................................................................................. ...................58 5.9 memory limit 0C1 ............................................................................................................ ....................59 5.10 i/o base 0C1 ............................................................................................................... .........................60 5.11 i/o limit 0C1.............................................................................................................. ...........................61 5.12 interrupt line, interrupt pin, and bridge control .......................................................................... ........62 5.13 subsystem vendor id and subsystem device id ................................................................................ 65 5.14 pc card 16-bit if legacy mode base address................................................................................. ..66 5.15 power management registers ................................................................................................. ............67 5.16 power management control and status ........................................................................................ ......68 5.17 dma slave con?guration register............................................................................................ ...........70 5.18 socket number .............................................................................................................. ......................71 5.19 con?guration miscellaneous 1 ............................................................................................... ..............73
advance data book v0.3 june 1998 4 table of contents cl-pd6833 pci-to-cardbus host adapter 6. cardbus registers ...................................................................................................... 75 6.1 status event pme_cxt ...................................................................................................... ............ 75 6.2 status mask pme_cxt....................................................................................................... ............ 77 6.3 present state ............................................................................................................... ........................ 78 6.4 event force ................................................................................................................. ......................... 80 6.5 control pme_cxt ........................................................................................................... ................ 82 7. operation registers ................................................................................................... 85 7.1 index ....................................................................................................................... ............................. 85 7.2 data........................................................................................................................ .............................. 90 8. device control registers........................................................................................ 91 8.1 chip revision ............................................................................................................... ........................ 91 8.2 interface status ............................................................................................................ ........................ 92 8.3 power control pme _cxt .................................................................................................... ........... 94 8.4 interrupt and general control pme_cxt..................................................................................... ... 96 8.5 card status change pme_cxt ................................................................................................ ...... 98 8.6 management interrupt con?guration pme_cxt............................................................................. 99 8.7 mapping enable .............................................................................................................. ...................101 9. window mapping registers..................................................................................... 103 9.1 i/o window mapping registers................................................................................................ ..........105 9.1.1 i/o window control ........................................................................................................ .......105 9.1.2 system i/o map 0C1 start address low ...............................................................................107 9.1.3 system i/o map 0C1 start address high ..............................................................................107 9.1.4 system i/o map 0C1 end address low ................................................................................108 9.1.5 system i/o map 0C1 end address high ...............................................................................108 9.1.6 card i/o map 0C1 offset address low .................................................................................109 9.1.7 card i/o map 0C1 offset address high ................................................................................109 9.2 memory window mapping registers ............................................................................................. ....110 9.2.1 system memory map 0C4 start address low.......................................................................110 9.2.2 system memory map 0C4 start address high......................................................................111 9.2.3 system memory map 0C4 end address low ........................................................................112 9.2.4 system memory map 0C4 end address high .......................................................................113 9.2.5 card memory map 0C4 offset address low .........................................................................114 9.2.6 card memory map 0C4 offset address high ........................................................................115 10. general window mapping registers.................................................................. 117 10.1 general mapping registers for i/o mode ..................................................................................... .....119 10.1.1 gen map 0C6 start address low (i/o)..................................................................................119 10.1.2 gen map 0C6 start address high (i/o).................................................................................120 10.1.3 gen map 0C6 end address low (i/o) ...................................................................................121 10.1.4 gen map 0C6 end address high (i/o) ..................................................................................122 10.1.5 gen map 0C6 offset address low (i/o)................................................................................123 10.1.6 gen map 0C6 offset address high (i/o) ...............................................................................124 10.2 general mapping register for memory mode ................................................................................... .125 10.2.1 gen map 0C6 start address low (memory) .........................................................................125 10.2.2 gen map 0C6 start address high (memory).........................................................................126 10.2.3 gen map 0C6 end address low (memory)...........................................................................127 10.2.4 gen map 0C6 end address high (memory)..........................................................................128 10.2.5 gen map 0C6 offset address low (memory)........................................................................129 10.2.6 gen map 0C6 offset address high (memory).......................................................................130
june 1998 5 advance data book v0.3 table of contents cl-pd6833 pci-to-cardbus host adapter 11. extension registers .................................................................................................131 11.1 misc control 1 ............................................................................................................. .......................132 11.2 fifo control ............................................................................................................... .......................134 11.3 misc control 2 ............................................................................................................. .......................136 11.4 chip information........................................................................................................... ......................137 11.5 ata control ................................................................................................................ ........................138 11.6 extended index ............................................................................................................. .....................140 11.7 extended data .............................................................................................................. .....................141 11.7.1 extension control 1...................................................................................................... .........142 11.7.2 gen map 0C6 upper address (memory) ...............................................................................143 11.7.3 pin multiplex control 0 register pme_cxt .....................................................................144 11.7.4 pin multiplex control 1 register pme_cxt .....................................................................146 11.7.5 gpio output control...................................................................................................... .......147 11.7.6 gpio input control....................................................................................................... .........147 11.7.7 gpio output data......................................................................................................... ........148 11.7.8 gpio input data.......................................................................................................... ..........148 11.8 prefetch window register ................................................................................................... ...............149 11.8.1 pci space control ........................................................................................................ ........149 11.8.2 pc card space control.................................................................................................... .....150 11.8.3 window type select ....................................................................................................... .......150 11.8.4 misc control 3 ........................................................................................................... ............151 11.8.5 smbus socket power control address pme_cxt ..........................................................153 11.8.6 gen map 0C6 extra control (i/o) .......................................................................................... 154 11.8.7 gen map 0C6 extra control (memory) ..................................................................................155 11.8.8 extension card status change............................................................................................. 156 11.8.9 misc control 4 ........................................................................................................... ............157 11.8.10 misc control 5 .......................................................................................................... .............158 11.8.11 misc control 6 .......................................................................................................... .............158 11.9 device identi?cation and implementation scheme ............................................................................1 59 11.9.1 mask revision byte....................................................................................................... ........159 11.9.2 product id byte .......................................................................................................... ...........160 11.9.3 device capability byte a ................................................................................................. ......161 11.9.4 device capability byte b ................................................................................................. ......162 11.9.5 device implementation byte a ............................................................................................. .163 11.9.6 device implementation byte b ............................................................................................. .164 11.9.7 device implementation byte c ............................................................................................. .165 11.9.8 device implementation byte d ............................................................................................. .166 12. timing registers...........................................................................................................1 67 12.1 setup timing 0C1 ........................................................................................................... ....................167 12.2 command timing 0C1 ......................................................................................................... ...............168 12.3 recovery timing 0C1 ........................................................................................................ .................169 13. dma operation registers.........................................................................................171 13.1 low address ................................................................................................................ ......................172 13.2 mid low address............................................................................................................ ....................172 13.3 mid high address........................................................................................................... ....................173 13.4 high address............................................................................................................... .......................173 13.5 low count .................................................................................................................. ........................174 13.6 mid count.................................................................................................................. .........................174 13.7 high count ................................................................................................................. ........................174
advance data book v0.3 june 1998 6 table of contents cl-pd6833 pci-to-cardbus host adapter 13.8 dma command and status ..................................................................................................... ..........175 13.9 request register ........................................................................................................... ....................176 13.10 mode register............................................................................................................. .......................177 13.11 master clear.............................................................................................................. .........................178 13.12 mask register ............................................................................................................. .......................178 14. ata mode operation ................................................................................................... 179 15. electrical specifications ...................................................................................... 181 15.1 absolute maximum ratings ................................................................................................... ............181 15.2 dc speci?cations........................................................................................................... ....................181 15.3 ac timing speci?cations .................................................................................................... ...............185 15.3.1 pci bus timing ........................................................................................................... ..........186 15.3.2 system interrupt timing .................................................................................................. ......191 15.3.3 pc card (pcmcia) bus timing calculations........................................................................192 15.3.4 pc card (pcmcia) bus timing ............................................................................................19 3 16. package specifications............................................................................................ 199 17. ordering information .............................................................................................. 201 a. pin listings................................................................................................................. .... 203 index.......................................................................................................................... ........ 211
june 1998 7 advance data book v0.3 conventions cl-pd6833 pci-to-cardbus host adapter 1. conventions this section presents conventions used in this document. general conventions bits within words and words within various memory spaces are generally numbered with 0 (zero) as the least-signi?cant bit or word. for example, the least-signi?cant bit of a byte is bit 0, and the most-signi?cant bit is bit 7. in addition, number ranges for bit ?elds and words are presented with the most-signi?cant value ?rst. thus, when discussing a bit ?eld within a register, the bit number of the most-signi?cant bit is written ?rst, followed by a colon (:), and then the bit number of the least-signi?cant bit; for example, bits 7:0. in this document, the names of the cl-pd6833 internal registers are boldface. for example, chip revision and power control are register names. the names of bit ?elds are written with initial uppercase letters. for example, card power on and battery voltage detect are bit ?eld names. abbreviations and acronyms the following table lists abbreviations and acronyms used in this document. acronym or abbreviation de?nition ac alternating current acpi advanced con?guration and power interface ata at-attachment cis card information structure dac digital-to-analog converter dc direct current dma direct memory access eeprom electrically erasable/programmable read-only memory eerom electrically erasable read-only memory gpio general-purpose i/o ide integrated device electronics irq interrupt request isa industry standard architecture jeida japanese electronic industry development association lqfp low-pro?le quad ?at pack lsb least-signi?cant bit mqfp metric quad ?at pack msb most-signi?cant bit mux multiplexer pci peripheral component interconnect pcm pulse coded modulation pcmcia personal computer memory card international association pme power management enable r2 release 2 (pc card 16) rfu reserved for future use ru read update sic serial interrupt controller smbus ? system management bus vga video graphics array zv zoomed video acronym or abbreviation de?nition (cont.)
advance data book v0.3 june 1998 8 conventions cl-pd6833 pci-to-cardbus host adapter measurement abbreviations numbers hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. for exam- ple, 14h and 03cah are hexadecimal numbers. binary numbers are enclosed in single quotation marks when in text. for example, 11 is a binary number. numbers not indicated by an h or single quotation marks are decimal. the use of tbd indicates values that are to be determined, n/a designates not available, and n/c indi- cates a pin that is a no connect. in addition, an uppercase x is used within numbers to indicate digits ignored by the cl-pd6833 within the current context. for example, 101xx01 is a binary number with bits 3:2 ignored. symbol units of measure c degree celsius gbyte gigabyte (2 30 or 1,073,741,824 bytes) hz hertz (cycle per second) kbyte kilobyte (2 10 or 1,024 bytes) khz kilohertz (1,000 hertz) mbyte megabyte (2 20 or 1,048,576 bytes) mhz megahertz (1,000,000 hertz) m a microampere m s microsecond (1,000 nanoseconds) ma milliampere ms millisecond (1,000 microseconds) ns nanosecond pf picofarad v volt
june 1998 9 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter 2. pin information the cl-pd6833 is packaged in a 208-pin mqfp (formerly pqfp) or lqfp (formerly vqfp) component package. the cl-pd6833 interface pins can be divided into four groups: l pci bus interface pins l pc card socket interface pins (two sets) l power control and general interface pins l power and ground pins refer to figures 2-1 and 2-2 for the cl-pd6833 pin diagrams. the pin assignments and descriptions for the four groups of interface pins are shown in table 2-1 through table 2-4 . refer to appendix a for pin listings using the pc card 16 (r2) and pc card 32 (cardbus) signal names in numerical and alphabetical order. also refer to appendix a for the pc card socket signal names and pci bus pin listing.
advance data book v0.3 june 1998 10 pin information cl-pd6833 pci-to-cardbus host adapter 2.1 pin diagrams figure 2-1. pin diagram for pc card 16 (r2) 160 159 158 157 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 64 65 67 68 69 70 71 72 73 74 75 66 98 99 100 101 102 103 104 122 124 125 126 127 128 129 130 105 131 132 133 134 156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 135 161 162 163 164 165 166 167 168 169 170 171 172 173 174 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 201 202 203 204 205 206 207 208 200 175 176 177 178 179 123 111 cl-pd6833 208-pin mqfp or lqfp +5v b_socket_vcc a_socket_vcc pci_vcc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1 b_a11 b_-iord b_a9 b_-iowr b_socket_vcc b_a8 b_a17 b_a13 b_a18 b_a14 b_a19 b_-we b_a20 b_rdy/-ireq b_a21 b_a16 b_a22 b_a15 b_a23 b_a12 ring_gnd b_a24 b_a7 b_a25 b_a6 b_vs2 b_a5 b_reset b_a4 b_-wait b_a3 b_-inpack b_a2 b_a1 b_bvd2/-spkr/-led b_a0 b_bvd1/-stschg/-ri b_d0 b_d8 b_d1 b_d9 b_d2 b_d10 b_wp/-iois16 b_-cd2 inta#/led1*/gpio1 intb#/ri_out*/pme# sout#/isld/irqser sin#/isdat/gpio2/led2 rst# b_-oe b_-ce2 b_a10 b_d15 b_-ce1 b_d14 b_d7 b_d13 b_d6 b_d12 b_d5 b_d11 b_d4 b_-cd1 b_d3 b_-reg# ring_gnd led_out*/hw_suspend#/pme#/gpio4 ? spkr_out*/gpio3 ? +5v a_-cd2 a_wp/-iois16 a_d10 a_d2 a_d9 a_d1 a_d8 a_d0 a_bvd1/-stschg/-ri a_a0 a_bvd2/-spkr/-led a_a1 a_a2 a_-inpack a_a3 a_-wait a_a4 a_reset a_a5 core_vdd b_vs1 a_a6 a_vs2 a_a7 a_a24 a_socket_vcc a_a12 a_a23 a_a15 a_a22 a_a16 a_a21 a_rdy/-ireq a_a20 a_-we a_a19 core_gnd a_a14 a_a18 a_a13 a_a17 a_a8 a_-iowr a_a9 a_-iord a_a11 a_vs1 a_-ce2 a_socket_vcc a_a10 a_d15 a_-ce1 a_d14 a_d13 a_d7 a_d6 a_d12 a_d5 a_d11 a_d4 a_-cd1 a_d3 a_-reg ad0 ring_gnd ad1 ad2 a_-oe ad3 pci_clk core_gnd ad31 ad30 ad29 pci_vcc ad28 ad27 ad26 ad25 ad24 c/be3# ring_gnd idsel ad23 ad22 ad21 ad20 ad19 pci_vcc ad18 ad17 ad16 c/be2# frame# ring_gnd irdy# trdy# devsel# stop# par c/be1# pci_vcc ad15 ad14 ad13 ad12 ad11 ad10 ring_gnd ad9 ad8 c/be0# ad7 ad6 pci_vcc ad5 ad4 perr# serr# a_a25 sclk sdata/smbdata ? slatch/smbclk ? gnt# req# clkrun# ring_gnd ring_gnd ring_gnd lock# a_socket_vcc core_vdd b_socket_vcc ring_gnd core_gnd core_vdd ring_gnd b_socket_vcc note: a double-dagger superscript ( ? ) at the end of the pin name indicates signals that are used for power-on con?guration switches.
june 1998 11 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter figure 2-2. pin diagram for pc card 32 (cardbus) 160 159 158 157 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 64 65 67 68 69 70 71 72 73 74 75 66 98 99 100 101 102 103 104 122 124 125 126 127 128 129 130 105 131 132 133 134 156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 135 161 162 163 164 165 166 167 168 169 170 171 172 173 174 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 201 202 203 204 205 206 207 208 200 175 176 177 178 179 123 111 cl-pd6833 208-pin mqfp or lqfp +5v b_socket_vcc a_socket_vcc pci_vcc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1 b_socket_vcc b_ccbe1# b_cad16 b_cpar b_rfu b_cperr# b_cblock# b_cgnt# b_cstop# b_cint# b_cdevsel# b_cclk b_ctrdy# b_cirdy# b_cframe# b_ccbe2# ring_gnd b_cad17 b_cad18 b_cad19 b_cad20 b_cvs2 b_cad21 b_crst# b_cad22 b_cserr# b_cad23 b_creq# b_cad24 b_cad25 b_caudio b_cad26 b_cstschg b_cad27 b_cad28 b_cad29 b_cad30 b_rfu b_cad31 b_cclkrun# b_ccd2# inta#/led1*/gpio1 intb#/ri_out*/pme# sout#/isld/irqser sin#/isdat/gpio2/led2 rst# b_ccbe3# a_cad20 a_cvs2 a_cad18 a_cad17 a_socket_vcc a_ccbe2# a_cframe# a_cirdy# a_ctrdy# a_cclk a_cdevsel# a_cint# a_cstop# a_cgnt# a_cblock# core_gnd a_cperr# a_rfu a_cpar a_cad16 a_ccbe1# a_cad15 a_cad14 a_cad13 a_cad12 a_cvs1 a_cad10 a_socket_vcc a_cad9 a_cad8 a_ccbe0# a_rfu a_cad6 a_cad7 a_cad5 a_cad4 a_cad3 a_cad2 a_cad1 a_ccd1# a_cad0 ad0 ring_gnd ad1 ad2 a_cad11 ad3 pci_clk core_gnd ad31 ad30 ad29 pci_vcc ad28 ad27 ad26 ad25 ad24 c/be3# ring_gnd idsel ad23 ad22 ad21 ad20 ad19 pci_vcc ad18 ad17 ad16 c/be2# frame# ring_gnd irdy# trdy# devsel# stop# par c/be1# pci_vcc ad15 ad14 ad13 ad12 ad11 ad10 ring_gnd ad9 ad8 c/be0# ad7 ad6 pci_vcc ad5 ad4 perr# serr# a_cad19 gnt# req# clkrun# ring_gnd ring_gnd lock# core_vdd core_gnd core_vdd ring_gnd b_socket_vcc b_cad12 b_cad13 b_cad14 b_cad15 b_cad11 b_cad10 b_cad9 b_cad8 b_ccbe0# b_rfu b_cad7 b_cad6 b_cad5 b_cad4 b_cad3 b_cad2 b_cad1 b_ccd1# b_cad0 ring_gnd led_out*/hw_suspend#/pme#/gpio4 spkr_out*/gpio3 +5v a_ccd2# a_cclkrun# a_cad31 a_d2 a_cad30 a_cad29 a_cad28 a_cad27 a_cstschg a_cad26 a_caudio a_cad25 a_cad24 a_creq# a_cad23 a_cserr# a_cad22 a_crst# a_cad21 core_vdd b_cvs1 a_ccbe3# sclk sdata/smbdata slatch/smbclk ring_gnd a_socket_vcc b_socket_vcc ring_gnd
advance data book v0.3 june 1998 12 pin information cl-pd6833 pci-to-cardbus host adapter 2.2 pin description conventions the following conventions apply to the pin description tables in section 2.3 : l a pound sign (#) at the end of a pin name indicates an active-low signal for the pci bus, cardbus, and pcmcia bus. l a dash (-) at the beginning of a pin name indicates an active-low signal for the pcmcia bus. l an asterisk (*) at the end of a pin name indicates an active-low signal that is a general interface for the cl-pd6833. l a double-dagger superscript ( ? ) at the end of the pin name indicates signals that are used for power-on con- ?guration switches. l a pin name ending in bracketed digits separated by a colon [n:n] indicates a multi-pin bus. l the pin number (pin number) column indicates the package pin that carries the listed signal. note that multi- pin buses are listed with the ?rst pin number corresponding to the most-signi?cant bit of the bus. for example, if pin numbers 4, 5, 7C12, 16C20, 22C24, 38C43, 45C46, 48C49, and 51C56 are associated with pci bus address input and data input/output pins ad[31:0], then the following pins correspond: ad31 is pin 4 ad1 is pin 55 ad0 is pin 56 l the quantity (qty.) column indicates the number of pins used (per socket where applicable). l the i/o-type code (i/o) column indicates the input and output con?gurations of the pins on the cl-pd6833. the possible types are de?ned below. l the power-type code (pwr.) column indicates the output drive power source for an output pin or the pull-up power source for an input pin on the cl-pd6833. the possible types are de?ned below. note: all pin inputs are referenced to core_vdd, independent of their output supply voltage. l the drive-type (drive) column describes the output drive-type of the pin (see dc speci?cations in chapter 15 for more information). note that the drive type listed for an input-only (i) pin is not applicable (C). i/o type description i input pin i-pu input pin with internal pull-up resistor o constant-driven output pin i/o input/output pin o-od open-drain output pin o-ts tristate output pin gnd ground pin pwr power pin power type output or pull-up power source 1 +5v: powered from a 5-volt power sup- ply (in most systems, see description of +5v pin in table 2-4 ) 2 a_socket_vcc: powered from the socket a v cc supply connecting to pc card pins 17 and 51 of socket a 3 b_socket_vcc: powered from the socket b v cc supply connecting to pc card pins 17 and 51 of socket b 4 pci_vcc: powered from the pci bus power supply 5 core_vdd: powered from a 3.3-volt power supply
june 1998 13 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter 2.3 pin descriptions table 2-1. pci bus interface pins pin name description pin number qty. i/o pwr. drive ad[31:0] pci bus address / data input/outputs: these pins connect to pci bus signals ad[31:0]. 4C5, 7C12, 16C20, 22C24, 38C43, 45C46, 48C49, 51C56 32 i/o 4 pci spec. c/be[3:0]# pci bus command / byte enables: the command signalling and byte enables are multiplexed on the same pins. during the address phase of a transaction, c/be[3:0]# are interpreted as the bus commands. during the data phase, c/be[3:0]# are interpreted as byte enables. the byte enables are valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path carry meaningful data for the current data phase. 13, 25, 36, 47 4 i/o 4 pci spec. frame# cycle frame: this signal, driven by current master, indicates that a bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is deasserted, the transaction is in its ?nal phase. 27 1 i/o 4 pci spec. irdy# initiator ready: this signal indicates the initiating agents ability to complete the current data phase of the transaction. irdy# is used in conjunction with trdy#. 29 1 i/o 4 pci spec. trdy# target ready: this signal indicates the target agents ability to complete the current data phase of the trans- action. trdy# is used in conjunction with irdy#. 30 1 i/o 4 pci spec. stop# stop: this signal indicates the current target is requesting the master to stop the current transaction. 32 1 i/o 4 pci spec. lock# lock transaction: this signal is used by a pci mas- ter to perform a locked transaction to a target memory. lock# is used to prevent more than one master from using a particular system resource. 58 1 i/o 4 pci spec idsel initialization device select: this input is used as a chip select during con?guration read and write trans- actions. this is a point-to-point signal. the cl-pd6833 must be connected to its own unique idsel line (from the pci bus arbiter or one of the most-signi?cant ad bus pins). 15 1 i C C devsel# device select: when actively driven, this signal indi- cates that it has decoded its own pci address as the target of the current access. as an input, devsel# indicates to the cl-pd6833 whether any device on the bus has been selected. 31 1 i/o 4 pci spec. perr# parity error: the cl-pd6833 drives this output active (low) if it detects a data parity error during a write phase. 33 1 i/o 4 pci spec.
advance data book v0.3 june 1998 14 pin information cl-pd6833 pci-to-cardbus host adapter serr# system error: this output is pulsed by the cl-pd6833 to indicate an address parity error. 34 1 o- od 4 pci spec. pa r parity: this pin is sampled by the clock cycle after completion of each corresponding address or write data phase. for read operations, this pin is driven from the cycle after trdy# is asserted until the cycle after completion of each data phase. it ensures even parity across ad[31:0] and c/be[3:0]#. 35 1 i/o 4 pci spec. pci_clk pci clock: this input provides timing for all transac- tions on the pci bus to and from the cl-pd6833. all pci bus interface signals described in this table ( table 2-1 ), except rst#, inta#, and intb# are sampled on the rising edge of pci_clk; and all the cl-pd6833 pci bus interface timing parameters are de?ned with respect to this edge. this input can be operated at frequencies from 0 to 33 mhz. 11iCC rst# device reset: this input is used to initialize all regis- ters and internal logic to their reset states and place all the cl-pd6833 pins in a high-impedance state. 207 1 i C C inta#/led1*/ gpio1 pci bus interrupt a: this output indicates a pro- grammable interrupt request generated from any of a number of card actions. although there is no speci?c mapping requirement for connecting interrupt lines from the cl-pd6833 to the system, a common use is to connect this pin to the pci bus inta# interrupt line and use pci interrupt signalling mode (see the register at memory offset 930h, misc control 5 on page 158 ). led1*: this feature is only available in pci/way inter- rupt signalling mode (see the register at memory off- set 930h, misc control 5 on page 158 ). general-purpose input/output 1: this pin can also be used for either input or output under the control of the gpio input control and gpio output control registers (see also the pin multiplex control 0 regis- ter at memory offset 914h). this pin is grouped with and powered from the pci_vcc pin. 203 1 o-ts 4 pci spec. intb#/ ri_out*/ pme# pci bus interrupt b: in pci interrupt signalling mode, this output can be used as an interrupt output connected to the pci bus intb# interrupt line. ring indicate output: if misc control 2 register bit 7 is 1, this pin works as a ring indicate output from a sockets bvd1/-stschg/-ri input. ring indicate capability is available in all of the interrupt signalling modes. ri_out* and intb# are open-drain outputs. power management event: this signal is used to indicate that a card or the controller needs service when it is in a power state that prohibits the use of an interrupt (see also the pin multiplex control 0 register at memory offset 914h). 204 1 od, o-ts 4 pci spec. table 2-1. pci bus interface pins (cont.) pin name description pin number qty. i/o pwr. drive
june 1998 15 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter clkrun# clock run: this pin is an input to indicate the status of pci_clk and an open-drain output to request the starting or speeding up of pci_clk. this pin com- plies with the pci mobile design guide . 208 1 i/o 4 pci spec. gnt# grant: this signal indicates that access to the bus has been granted. 21iCC req# request: this signal indicates to the arbiter that the cl-pd6833 requests use of the bus. 31o4 pci spec. pci_vcc pci bus v cc : these pins can be connected to either a 3.3- or 5-v power supply. the pci bus interface pin outputs listed in this table ( table 2-1 ) operate at the voltage applied to these pins, independent of the volt- age applied to other cl-pd6833 pin groups. 6, 21, 37, 50 4 pwr C C table 2-2. socket interface pins pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b -reg/ ccbe3# register access: during pc card 16 memory cycles, this output chooses between attribute and common memory. during i/o cycles for non-dma transfers, this signal is active (low). during ata mode, this signal is always inactive. for dma cycles on the cl-pd6833 to a dma- capable card, -reg is inactive during i/o cycles to indicate dack to the pc card 16. in cardbus mode, this pin is the command and byte enable 3. 112 188 1 i/o 2 or 3 card- bus spec. a[25:24]/ cad[19, 17] pc card 16 socket address 25:24 outputs. in cardbus mode, these pins are the cardbus address/data bits 19 and 17, respectively. 102, 99 176, 174 2 i/o 2 or 3 card- bus spec a23/ cframe# pc card 16 socket address 23 output. in cardbus mode, this pin is the cardbus frame# signal. 96 172 1 i/o pu 2 or 3 card- bus spec a22/ ctrdy# pc card 16 socket address 22 output. in cardbus mode, this pin is the cardbus trdy# signal. 94 170 1 i/o pu 2 or 3 card- bus spec 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 . table 2-1. pci bus interface pins (cont.) pin name description pin number qty. i/o pwr. drive
advance data book v0.3 june 1998 16 pin information cl-pd6833 pci-to-cardbus host adapter a21/ cdevsel# pc card 16 socket address 21 output. in cardbus mode, this pin is the cardbus devsel# signal. 92 168 1 i/o pu 2 or 3 card- bus spec a20/ cstop# pc card 16 socket address 20 output. in cardbus mode, this signal is the card- bus stop# signal. 90 166 1 i/o pu 2 or 3 card- bus spec a19/ cblock# pc card 16 socket address 19 output. in cardbus mode, this signal is the card- bus lock# signal used for locked trans- actions. 88 164 1 i/o pu 2 or 3 card- bus spec a18/ rfu pc card 16 socket address 18 output. in cardbus mode, this pin is reserved for future use. 85 161 1 o 2 or 3 card- bus spec a17/ cad16 pc card 16 socket address 17 output. in cardbus mode, this pin is the cardbus address/data bit 16. 83 158 1 i/o 2 or 3 card- bus spec a16/ cclk pc card 16 socket address 16 output. in cardbus mode, this pin supplies the clock to the inserted card. 93 169 1 o 2 or 3 clock spec. a15/ cirdy# pc card 16 socket address 15 output. in cardbus mode, this pin is the cardbus irdy# signal. 95 171 1 i/o pu 2 or 3 card- bus spec. a14/ cperr# pc card 16 socket address 14 output. in cardbus, this pin is the cardbus perr# signal. 86 162 1 i/o pu 2 or 3 card- bus spec. a13/ cpar pc card 16 socket address 13 output. in cardbus mode, this pin is the cardbus par signal. 84 159 1 i/o 2 or 3 card- bus spec. a12/ ccbe2# pc card 16 socket address 12 output. in cardbus mode, this pin is the command and byte enable 2. 97 173 1 i/o 2 or 3 card- bus spec. a[11:9]/ cad[12, 9, 14] pc card 16 socket address 11:9 outputs. in cardbus mode, these pins are the cardbus address/data bits 12, 9, and 14, respectively. 77, 73, 80 153, 149, 155 3 i/o 2 or 3 card- bus spec. a8/ ccbe1# pc card 16 socket address 8 output. in cardbus mode, this pin is the command and byte enable 1. 82 157 1 i/o 2 or 3 card- bus spec. table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
june 1998 17 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter a[7:0]/ cad[26:20, 18] pc card 16 socket address 7:0 outputs. in cardbus mode, these pins are the cardbus address/data bits 18 and 20C26, respectively. 100, 103, 105, 107, 109, 111, 113, 116 175, 178, 181, 183, 185, 187, 189, 191 8 i/o 2 or 3 card- bus spec. d15/ cad8 pc card 16 socket data i/o bit 15. in cardbus mode, this pin is the cardbus address/data bit 8. 71 148 1 i/o 2 or 3 card- bus spec. d14/ rfu pc card 16 socket data i/o bit 14. in cardbus mode, this pin is reserved for future use. 69 145 1 i/o 2 or 3 card- bus spec. d[13:3]/ cad[6, 4, 2, 31, 30, 28, 7, 5, 3, 1, 0] pc card 16 socket data i/o bits 13:3. in cardbus mode, these pins are the cardbus address/data bits 6, 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0, respectively. 67, 65, 63, 124, 122, 120, 68, 66, 64, 62, 59 142, 140, 138, 199, 197, 195, 144, 141, 139, 137, 135 11 i/o 2 or 3 card- bus spec. d2/ rfu pc card 16 socket data i/o bit 2. in cardbus mode, this pin is reserved for future use. 123 198 1 i/o 2 or 3 card- bus spec. d[1:0]/ cad[29, 27] pc card 16 socket data i/o bits 1:0. in cardbus mode, these pins are the cardbus address/data bits 29 and 27, respectively. 121, 119 196, 194 2 i/o 2 or 3 card- bus spec. -oe/ cad11 output enable : this output goes active (low) to indicate a memory read from the pc card 16 socket to the cl-pd6833. in cardbus mode, this pin is the cardbus address/data bit 11. 75 151 1 i/o 2 or 3 card- bus spec. -we/ cgnt# write enable : this output goes active (low) to indicate a memory write from the cl-pd6833 to the pc card 16 socket. in cardbus mode, this pin is the cardbus gnt# signal. 89 165 1 o 2 or 3 card- bus spec. -iord/ cad13 i/o read : this output goes active (low) for i/o reads from the socket to the cl-pd6833. in cardbus mode, this pin is the cardbus address/data bit 13. 78 154 1 o-ts 2 or 3 card- bus spec. -iowr/ cad15 i/o write : this output goes active (low) for i/o writes from the cl-pd6833 to the socket. in cardbus mode, this pin is the cardbus address/data bit 15. 81 156 1 i/o 2 or 3 card- bus spec. table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
advance data book v0.3 june 1998 18 pin information cl-pd6833 pci-to-cardbus host adapter wp/ -iois16/ cclkrun# write protect / i/o is 16-bit : in memory card interface mode, this input is inter- preted as the status of the write protect switch on the pc card 16. in i/o card interface mode, this input indicates the size of the i/o data at the current address on the pc card 16. in cardbus mode, this pin is the cardbus clkrun# signal, which starts and stops the cardbus clock (cclk). 125 201 1 i/o- pu 2 or 3 card- bus spec. -inpack/ creq# input acknowledge: the -inpack function is not applicable in pci bus environments. this pin should be connected to the pc card sockets -inpack pin, since this can be the dreq signal during dma cycles. in cardbus mode, this pin is the cardbus req# signal. 110 186 1 i-pu 2 or 3 C rdy/ -ireq/ cint# ready / interrupt request: in memory card interface mode, this input indicates to the cl-pd6833 that the card is either ready or busy. in i/o card interface mode, this input indicates a card interrupt request. in cardbus mode, this pin is the cardbus interrupt request signal. this signal is active-low and level-sensitive. 91 167 1 i-pu 2 or 3 C -wait/ cserr# wait: this input indicates a request by the card, to the cl-pd6833, to halt the cycle in progress until this signal is deactivated. in cardbus mode, this pin is the cardbus serr# signal. 108 184 1 i-pu 2 or 3 C -cd[2:1]/ ccd[2:1]# card detect: these inputs indicate to the cl-pd6833 that a card is in the socket. they are internally pulled high to the volt- age of the +5v power pin. in cardbus mode, these inputs are used in conjunction with cvs[2:1] to detect the presence and type of card. 126, 61 202, 136 2 i-pu 1 C table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
june 1998 19 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter -ce2/ cad10 card enable: this pin is driven low by the cl-pd6833 during card access cycles to control byte/word card access. -ce1 enables even-numbered address bytes, and -ce2 enables odd-numbered address bytes. when con?gured for 8-bit cards, only -ce1 is active and a0 is used to indi- cate access of odd- or even-numbered bytes. in cardbus mode, this pin is the cardbus address/data bit 10. 74 150 1 i/o 2 or 3 card- bus spec. -ce1/ ccbe0# card enable: this pin is driven low by the cl-pd6833 during card access cycles to control byte/word card access. -ce1 enables even-numbered address bytes, and -ce2 enables odd-numbered address bytes. when con?gured for 8-bit cards, only -ce1 is active and a0 is used to indicate access of odd- or even-numbered bytes. in cardbus mode, this pin is the command and byte enable 0. 70 147 1 i/o 2 or 3 card- bus spec. reset/ crst# card reset: this output is low for normal operation and goes high to reset the card. to prevent reset glitches to a card, this signal is high-impedance unless a card is seated in the socket, card power is applied, and the cards interface signals are enabled. in cardbus mode, this pin is the rst# input to the card, which is active-low. 106 182 1 o-ts 2 or 3 card- bus spec. bvd2/ -spkr/ -led/ caudio battery voltage detect 2 / speaker / led: in memory card interface mode, this input serves as the bvd2 (battery warning status) input. in i/o card interface mode, this input can be con?gured as a cards - spkr binary audio input. for ata or non- ata (sff-68) disk-drive support, this input can also be con?gured as a drive-status led input. in cardbus mode, this pin is the audio input from the card. 114 190 1 i-pu 2 or 3 C table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
advance data book v0.3 june 1998 20 pin information cl-pd6833 pci-to-cardbus host adapter bvd1/ -stschg/ -ri / cstschg battery voltage detect 1 / status change / ring indicate: in memory card interface mode, this input serves as the bvd1 (battery-dead status) input. in i/o card interface mode, this input is the -stschg input, which indicates to the cl-pd6833 that the cards internal status has changed. if bit 7 of the interrupt and general control register is set to 1, this pin serves as the ring indicate input for wakeup-on-ring system power manage- ment support. in cardbus mode, this pin is the cardbus status change used by the card to alert the system to changes in ready, wp, and bvd[2:1]. 118 192 1 i-pu 2 or 3 C vs2/ cvs2 voltage sense 2: this pin is used in conjunction with vs1 to determine the operating voltage of the card. this pin is internally pulled high to the voltage of the +5v power pin under the combined control of the external data write bits and the cd pull-up control bits. this pin connects to pc card 16 socket pin 57. in cardbus mode, this is cardbus voltage sense 2. it is used in conjunction with cvs1, ccd1, and ccd2 to determine the initial voltage applied to the cardbus pc card. 104 179 1 i/o 1 2 ma vs1/ cvs1 voltage sense 1: this pin is used in con- junction with vs2 to determine the operat- ing voltage of the card. this pin is inter- nally pulled high to the voltage of the +5v power pin under the combined control of the external data write bits and the cd pull-up control bits. this pin connects to pc card 16 socket pin 43. in cardbus mode, this is cardbus voltage sense 1. it is used in conjunction with cvs2, ccd1, and ccd2 to determine the initial voltage applied to the cardbus pc card. 76 152 1 i/o 1 2 ma table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
june 1998 21 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter socket_vcc connect these pins to the v cc supply of the socket (pins 17 and 51 of the respec- tive pc card 16 socket). these pins can be 0, 3.3, or 5 v, depending on card pres- ence, card type, and system con?guration. the socket interface outputs (listed in this table, table 2-2 ) operate at the voltage applied to these pins, independent of the voltage applied to other cl-pd6833 pin groups. 117, 98, 60 200, 160, 143 3 pwr C C table 2-3. power control and general interface pins pin name description pin number qty. i/o pwr. drive spkr_out* /gpio3 ? speaker output: this output can be used as a digital output to a speaker to allow a system to support pc card 16 fax/modem/voice and audio sound output. this output is enabled by setting the sockets misc control 1 register bit 4 to 1 (for the socket whose speaker signal is to be directed from bvd2/-spkr/-led to this pin). this pin is used for con?guration information during hardware reset. refer to misc control 3 register bit 0. general-purpose input/output 3: this pin can also be used for either input or output under the control of the gpio input control and gpio output control registers (see also the pin multiplex control 0 register at memory offset 914h). this pin is grouped with and powered from the +5v pins. 128 1 i/o 1 8 ma table 2-2. socket interface pins (cont.) pin name 1 description 2 pin number qty. i/o pwr. drive socket a socket b 1 to differentiate the sockets in the pin diagram, all socket-speci?c pins have either a_ or b_ prepended to the pin names indi- cated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see chapter 14 .
advance data book v0.3 june 1998 22 pin information cl-pd6833 pci-to-cardbus host adapter led_out*/ hw_suspend#/ pme#/gpio4 ? led output: this output can be used as an led driver to indicate disk activity when a sockets bvd2/-spkr/-led pin has been programmed for led support. the extension control 1 register bit 2 must be set to 1 to enable this output (to re?ect any activity on bvd2/-spkr/-led), and a sockets ata control register bit 1 must be set to 1 to allow the level of the bvd2/-spkr/-led pin to re?ect disk activity. serves as a hw_suspend# input pin, when misc control 3 register bit 4 is set to 1. this pin is used for con?guration information during hardware reset. refer to misc control 3 register bit 1. general-purpose input/output 4: this pin can also be used for either input or output under the control of the gpio input control and gpio output control registers. this pin is grouped with and powered from the +5v pins. power management event: this signal is used to indicate that a card or the controller needs service and is in a power state that prohibits the use of an interrupt (see also the pin multiplex control 0 register at memory offset 914h). 133 1 i/o 1 8 ma sclk serial clock: this input is used as a reference clock (10C100 khz, usually 32 khz) to control the serial interface of the socket power control chips. caution: this pin must be driven at all times. see section 3.1.7.1 on page 35 for more information on socket power control. 132 1 i C C s data / smbdata ? serial data / system management bus data: this pin serves as output pin sdata when used with the serial interface of texas instruments tps2206aidf socket power control chip, and serves as a bidirectional pin smbdata when used with intels system management bus used by maxims socket power control chip. this pin is open drain for the smbus mode of opera- tion and requires an external pull-up. this pin is used to detect power-up during reset (see section 3.2 on page 38 ). 131 1 i/o 1 8 ma (for s data ) table 2-3. power control and general interface pins (cont.) pin name description pin number qty. i/o pwr. drive
june 1998 23 advance data book v0.3 pin information cl-pd6833 pci-to-cardbus host adapter slatch/ smbclk ? serial latch / system management bus clock: this pin serves as output pin slatch when used with the serial interface of texas instruments tps2206aidf socket power control chip, and serves as bidirectional pin smbclk when used with intels system management bus used by maxims socket power control chip. this pin is open drain in the smbus mode of operation. in this mode an external pull up is required. this pin is used for con?guration information during hardware reset. refer to misc control 3 register bit 2. 130 1 i/o- pu 1 8 ma (for slatch) sout#/isld/ irqser serial interrupt output / serial irq load: in pci interrupt signalling mode, this pin is a no- connect. in pc/pci serial interrupt signalling mode, this pin is the serial interrupt output, sout#. in pci/way interrupt signalling mode, this pin is the irqser signal, which is bidirectional. in external-hardware interrupt signalling mode, this pin is the load signal, isld, used to load the serially transmitted interrupt data into the exter- nal serial-to-parallel shifters. 205 1 i/o 4 pci spec. sin#/isdat/ gpio2/led2 serial interrupt input / serial irq data: in pci interrupt signalling mode, this pin is a no- connect. in pc/pci serial interrupt signalling mode, this pin is the serial interrupt input, sin# (see the register at memory offset 930h, misc control 5 on page 158 ). in external-hardware interrupt signalling mode, this pin is the irq vector data, isdat, that is serially transmitted to the external serial-to- parallel shifters. general-purpose input/output 2: this pin can also be used for either input or output under the control of the gpio input control and gpio output control registers (see also the pin multiplex control 0 register at memory offset 914h). this pin is grouped with and powered from the pci_vcc pin. led2: this feature is only available in pci/way interrupt signalling mode (see the register at memory offset 930h, misc control 5 on page 158 ). 206 1 i/o 4 pci spec. table 2-3. power control and general interface pins (cont.) pin name description pin number qty. i/o pwr. drive
advance data book v0.3 june 1998 24 pin information cl-pd6833 pci-to-cardbus host adapter table 2-4. power and ground pins pin name description pin number qty. i/o pwr. drive +5v this pin is connected to the systems 5-v power supply. 127 1 pwr C C core_vdd this pin provides power to the core circuitry of the cl-pd6833. this pin must be connected to the 3.3-v supply. 134, 79, 180 3 pwr C C core_gnd all the cl-pd6833 ground lines should be con- nected to system ground. 26, 87, 177 3 gnd C C ring_gnd all the cl-pd6833 ground lines should be con- nected to system ground. 14, 28, 44, 57, 72, 101, 115, 129, 146, 163, 193 11 gnd C C
june 1998 25 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3. introduction to the cl-pd6833 3.1 system architecture this section describes the cl-pd6833 basic architecture in terms of pc card functions. it ?rst introduces pc cards, the pcmcia (personal computer memory card international association), and the pc card standard, and then discusses how the cl-pd6833 complies with the standards. it also describes the windowing capabilities of the cl-pd6833. 3.1.1 pc card basics pc cards are credit-card-size peripherals that add memory and i/o capabilities to computers in a rugged, compact form factor. the pc card standard describes speci?cations for using these memory and i/o devices as insertable, exchangeable peripherals for personal and handheld computers. the pc card standard is published by the pcmcia, a non-pro?t trade association that promotes pc card technology by de?ning technical standards. there are two types of pc cards: pc card 16 (r2) and pc card 32 (cardbus). pc card 16 (r2) cards are 16-bit cards that comply with pcmcia standard releases 2.0, 2.01, and 2.1. in 1995, the pcmcia released a standard for pc cards in conjunction with the standard for the pc card 16 (r2) architecture, and renamed the joint standard as pc card standard. this joint standard introduced 32-bit operation and support for pc card 32 (cardbus) bus mastering cards. pc card 32 (cardbus) cards are 32-bit cards that comply with the pc card standard ?rst released in february 1995. the cl-pd6833 implements both pc card 16 (r2) and pc card 32 (cardbus) functions. the r2 functions of the cl-pd6833 implement the functions described in the pcmcia standard release 2.1, while the cardbus functions of the cl-pd6833 are compatible with the pc card standard. under software control, the cl-pd6833 uses the vs1, vs2, cd1, and cd2 pins in the manner described by the pc card standard to identify and power up the pc card. the pc card type (r2 or cardbus) determines its voltage requirements. for simpler end-user and vendor implementation of the standard, systems employing the pc card standard should also be backward-compatible with industry-standard pc addressing. the cl-pd6833 is backward-compatible with pcmcia standard releases 1.0, 2.0, 2.01, and 2.1. the cl-pd6833 is also compatible with jeida 4.1 and earlier standards corresponding with the pcmcia standards above. pc card 16 (r2) cards can have attribute and common memory. attribute memory indicates to host soft- ware the capabilities of the pc card, and it allows host software to change the con?guration of the card. common memory can be used by host software for any purpose such as ?ash ?le system, system mem- ory, and ?oppy emulation. for memory-type pc card 16 (r2) cards, the memory information must be mapped into the system mem- ory address space. this is accomplished with a windowing technique that is similar to expanded memory schemes already used in pc systems (for example, lim 4.0 memory manager). i/o-type pc card 16 (r2) cards, such as modems, should also be directly addressable, as if the cards were i/o devices plugged into the pci bus. for example, it would be highly desirable to have a pc card modem accessible to standard communications software as if it were at a com port. for com1, this would require that the modem be accessed at system i/o address 3f8hC3ffh. the method of mapping a pc card i/o address into anticipated areas of pci i/o space is similar to memory windowing.
advance data book v0.3 june 1998 26 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.1.2 cl-pd6833 r2 windowing capabilities for full compatibility with existing software and to ensure compatibility with future r2 memory card and r2 multifunction i/o cards, the cl-pd6833 provides seven programmable general-purpose windows per socket. these windows default at reset to two i/o windows and ?ve memory windows. any one of the seven windows can be programmed to respond on the pci primary bus as either a memory or i/o window and to issue either a memory or i/o cycle to the r2-compatible pc card. for example, in the case of a non-x86 processor that must memory map i/o devices, a window would be set for memory on the primary pci side and i/o on the r2-compatible pc card side. tables 3-1 and 3-2 show the programming options for each memory and i/o window. table 3-1. memory window options memory window option description enable each of the seven windows can be programmed as a memory window and individually enabled. devsel# is not asserted for disabled windows. start address this is the start address of the memory window within the selected 16-mbyte page of pci memory. the start address can be programmed to reside on any 4-kbyte boundary within the programmed page of pci memory. end address this is the end address of the memory window within the selected 16-mbyte page of pci memory. the end address can be programmed to reside on any 4-kbyte boundary within the programmed page of pci memory. only memory accesses between the start and end address get a response. offset address the offset address is added to the pci address to determine the address for accessing the pc card. this allows the addresses in the pc card address space to be different from the pci address space. upper address the upper memory address speci?es a 16-mbyte page of pci memory. data size the size of accesses can be set manually to either 8 or 16 bits. timing the timing of accesses (setup/command/recovery) can be set by either of two timing register sets: timer set 0 or timer set 1 . register access setting the reg# pin can be enabled on a per-window basis so that any of the windows can be used for accessing attribute memory. write protect if the window is programmed to be write-protected, then writes to the memory window are ignored (reads are still performed normally).
june 1998 27 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter caution: the windows of the cl-pd6833 should never be allowed to overlap with each other or the other devices in the system. this would cause signal collisions and result in erratic behavior. figure 3-1. memory-to-memory window organization table 3-2. i/o window options i/o window option description enable each of the seven windows can be programmed as an i/o window and individually enabled. start address the start address of the window is programmable on single-byte boundaries from 0 to 64 kbytes. end address the end address of the window is also programmable on single-byte boundaries from 0 to 64 kbytes. offset address the offset address is added to the pci address to determine the address for accessing the pc card. auto size the size of accesses can be set automatically, based on the pc card -iois16 signal. data size the size of accesses can be set manually to either 8 or 16 bits, overriding the auto size option. timing the timing of accesses (setup/command/recovery) can be set by either of two timing register sets: timer set 0 or timer set 1 . pci memory address space pc card memory address space memory common memory attribute memory . . . . 16-mbyte page card memory map system memory map system memory map system memory map upper address register end address registers start address registers offset address registers card memory window memory window 4 gbytes 64 mbytes . . . . page 0 page 1 page 255 note: pci memory window can map to either common or attribute pc card memory. (selects 16-mbyte page)
advance data book v0.3 june 1998 28 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter figure 3-2. r2 i/o-to-i/o window organization figure 3-3. memory-to-i/o window organization pci i/o address space pc card i/o address space card i/o window 64 mbytes 4 gbytes* . . . . system i/o map end address registers system i/o map start address registers system i/o map upper address registers card i/o map offset address registers i/o window uses 0 for 64 kbytes sup- ported by the cl-pd6833 *note: the cl-pd6833 only decodes the ?rst 64 kbytes of the pci i/o space. 64 kbytes pci memory address space pc card i/o address space memory . . . . 16-mbyte page card i/o map system memory map system memory map system memory map upper address register end address registers start address registers offset address registers card i/o window memory window 4 gbytes 64 mbytes . . . . page 0 page 1 page 255 (selects 16-mbyte page)
june 1998 29 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter figure 3-4. r2 i/o-to-memory window organization 3.1.3 zoomed video port the cl-pd6833 supports the implementation of the zv (zoomed video) port at the pc card interface. the zv port provides a direct connection between a pc card, a vga controller, and an audio dac. it allows the pc card to directly write video data to a graphics controller input port and audio data to a dig- ital-to-analog converter. the cl-pd6833 supports the zv port in the bypass mode, during which the signals are directly routed from the pc card bus to the video port of the vga controller. rerouting is accomplished by tristating address lines a[25:4] from the cl-pd6833. the cl-pd6833 enters the zv port mode when the multimedia enable bit (bit 0 of the misc control 1 register at index 16h or memory offset 816h) is set to a 1. the cl-pd6833 has a multimedia arm bit (bit 7 of the misc control 3 register at i/o index 2fh, extended index 25h, or memory offset 925h), which works as an overriding control bit. until the multimedia arm bit is set, the multimedia enable bit does not tristate the address pins as previously described. figure 3-5 shows an example of the zv port implementation using the cl-pd6833. for more details, refer to the application note zoomed video port implementation (an-pd10). pci i/o address space pc card memory address space system i/o map system i/o map end address registers start address registers i/o window 64 mbytes 4 gbytes* card memory map offset address registers . . . . common memory attribute memory card memory window 64 kbytes *note: the cl-pd6833 only decodes the ?rst 64 kbytes of the pci i/o space.
advance data book v0.3 june 1998 30 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter figure 3-5. a typical zv port implementation 3.1.4 interrupts the i/o-type pc cards usually have interrupts that need to be serviced by host software. for example, for a modem card accessed as if at com1, the software would expect the modem to generate interrupts on the irq4 line. to be sure all interrupts are routed as expected, the cl-pd6833 can steer the interrupt from the pc card to one of the four pci-bus-de?ned interrupts or to one of several standard pc interrupts. the cl-pd6833 supports four interrupt schemes: pci interrupt, intels pc/pci serial interrupt, pci/way interrupt, and external-hardware interrupt. the cl-pd6833 allows sharing of interrupts under software control. this is accomplished by programming the cl-pd6833 to alternately pulse and then tristate the desired interrupt pin. in addition, the cl-pd6833 allows two i/o devices to share one interrupt line in systems that have only one interrupt line and all interrupt requests are routed to that one interrupt line. for example, if two fax/modem cards are inserted into the dual- socket pc card controller, and both are active and share the only interrupt line provided by the host system, then the application software can still identify the requester and the type of the pending interrupt. dram cl-gd7xxx analog encoder cl-pd6833 video decoder pcm converter pc card interface pc card motherboard audio video ntsc/pal rf signal audio video & control 4 19 pc card slot tv lcd crt amp audio codec speakers 4 pcm audio input 19 zv port (video) pci bus
june 1998 31 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter the cl-pd6833 supports two classes of interrupts: l socket or card functional interrupts (initiated by the pc card activating its rdy/-ireq signal) l management interrupts (triggered by changes in pc card status) there are four changes in pc card status that can be programmed to cause management interrupts: l card insertion or removal l battery dead indicator (bvd1) or i/o-type card status change (-stschg) l battery warning indicator (bvd2) change on a memory-type card l ready (rdy) status change on a memory-type card any interrupt from either class of interrupts can be steered by the cl-pd6833 to any interrupt output. this is useful because irq-type interrupts in pc-compatible systems are not generally shared by hardware. therefore, each device in the system using irq-type interrupts must have a unique interrupt line. addi- tionally, many software applications assume that certain i/o devices use speci?c irq signals. to allow pc cards with differing i/o functionality to be connected to appropriate non-con?icting irq locations, the cl-pd6833 can steer the interrupt signal from a pc card to any one of ten interrupt outputs. the cl-pd6833 provides four pins for interrupts. these pins have multiple functionality to allow the cl-pd6833 to output a number of speci?c interrupts, depending on which of four interrupt signalling modes is selected: l pc/pci interrupt signalling mode l external-hardware interrupt signalling mode l pci/way interrupt signalling mode l pci interrupt signalling mode the interrupt signalling mode is usually established during power-on reset by the level of pins 133 (led_out*/hw_suspend#) and 128 (spkr_out*), but it can also be set by writing to bits 1:0 of the misc control 3 register (memory offset 925h). refer to table 3-3 for the interrupt signalling mode con?guration. note that depending on the mode, the intb#/ri_out* pin can be con?gured to function as a ring indica- tor output (ri_out*) to an 80360-type chip sets -ri input. when con?gured in ring indicate mode by programming bit 7 of the misc control 2 register (memory offset 81eh) to 1, outputs from an i/o-type cards -stschg pin 1 are passed through to the intb#/ri_out* pin of the cl-pd6833. note: this does not apply if the cl-pd6833 is programmed for pme. 1 interrupt and general control register bits 5 and 7 must be set to 1s for a socket interface to accept an -ri input. table 3-3. interrupt signalling mode con?guration mode led_out*/ hw_suspend# spkr_out* misc control 3 (pin 133) (pin 128) bit 1 bit 0 pc/pci pull-down pull-down 0 0 external-hardware pull-down pull-up 0 1 pci/way pull-up pull-down 1 0 pci pull-up pull-up 1 1
advance data book v0.3 june 1998 32 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter external-hardware interrupt signalling mode in this mode, up to eight isa irq interrupts and two pci interrupts are supported. two pins (pin 205 functioning as isld and pin 206 functioning as isdat) interface with external hardware, which converts the signals to appropriate isa-type irq totem-pole interrupt outputs. figure 3-6. external-hardware interrupt signalling mode the interrupts are serially passed on the isdat pin to the external hardware. the interrupts are shifted into the external serial-to-parallel converter using pci_clk. the interrupts are latched using the isld signal. in this mode, pin 203 functions as inta#, and pin 204 functions as intb#/ri_out*. refer to application note interrupt signalling modes for the cl-pd6730 and cl-pd6832 (an-pd8) . this is the only mode that supports pulse mode interrupts. the cl-pd6833 contains unique logic that allows isa-style, irq-type interrupts to be shared under software control. this is accomplished by programming the cl-pd6833 to alternately pulse and then tristate the desired interrupt pin, which is programmed as an irq-type output. this unique irq interrupt sharing technique requires additional software to allow for the sharing of interrupts. pci/way interrupt signalling mode this mode of operation uses the pci/way single-pin interrupt system. in this mode one pin (pin 205) inter- faces with a pci/wayCcompliant motherboard chip set. figure 3-7. pci/way serial interrupt signalling mode the sout#/isld/irqser pin on the cl-pd6833 is the bidirectional serial interrupt line. in this mode, pin 203 works as inta# and pin 204 works as intb#/ri_out*. pin 206 is not used. cl-pd6833 irq3 irq4 irq5 irq7 irq11 irq12 irq14 irq15 inta# intb#/ri_out* pci_clk cl-pd6701 sin#/isdat (206) sout#/isld (205) intb#/ri_out* (204) inta# (203) isdat isld cl-pd6833 irqser intb#/ri_out* pci_clk sin#/isdat (206) sout#/isld (205) intb#/ri_out* (204) inta# (203) inta# irqser motherboard chip set
june 1998 33 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter pci interrupt signalling mode this is the default mode, as per the power-on-reset condition of the misc control 3 register. it uses pins 203 and 204 directly as the pci-type int# open-drain interrupts (refer to figure 3-8 ). if the cl-pd6833 is not programmed for ring indicate, inta# is used for function 0 and intb# is used for function 1. if the cl-pd6833 is programmed for ring indicate, inta# is used for both function 0 and 1. ring-indicate output appears on intb#. programming pc card interrupts ( interrupt and general control register, index 3h) or management interrupts ( management interrupt con?guration register, index 5h) does not affect pci mode. figure 3-8. pci interrupt signalling mode (a common interrupt mapping) pc/pci serial interrupt signalling mode this mode supports the mobile pc/pci extended interrupt programming model. in this mode, two pins (pin 205 functioning as sout# and 206 functioning as sin#) interface with an sic (serial interrupt con- troller). the number of interrupts supported depends on the sic con?guration. figure 3-9. pc/pci serial interrupt signalling mode the sin# pin on the cl-pd6833 is the serial interrupt input line from other devices in the interrupt loop, and the sout# pin is the serial interrupt output line containing the logical and of the interrupt level in the cl-pd6833, along with sin# interrupts. the sic is clocked by pci_clk, and clkrun# is used by the cl-pd6833 to restart pci_clk if it has stopped. in this mode, pin 204 is intb#/ri_out* and pin 203 is inta#. program misc control 2 register bit 7 to 1 for ring indicate function. inta# intb#/ri_out* cl-pd6833 intb#/ri_out* (204) inta# (203) pci bus ? y ? cl-pd6833 sic sin# sout# intb#/ri_out* pci_clk sin#/isdat (206) sout#/isld (205) intb#/ri_out* (204) inta# (203) irq[x] inta#
advance data book v0.3 june 1998 34 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.1.5 pci/way dma the cl-pd6833 supports the pci/way dma (direct memory access). this dma approach is applicable to a pc system that does not have an isa bus as its main system bus. the approach requires that two or more devices (on a non-isa bus) support legacy dma. since the pci/way dma speci?cation describes an approach that distributes independent, standard programming model bus-master channels among devices, it is also popularly known as distributed dma. the cl-pd6833 provides complete, seamless support for dma-capable pc cards on the pcmcia bus as outlined in the pc card standard. when a dma-capable pc card requests dma operation, the cl-pd6833 uses the req#, gnt# protocol on the pci bus to handle the dma transfer. programming registers in the cl-pd6833 re?ects the functions found in the legacy 8237 dma controller chip. 3.1.6 power management the cl-pd6833 employs power management techniques to provide long battery life. this is achieved by minimizing the power consumption of the cl-pd6833 and that of the pc cards. substantial power is saved by turning off the pci_clk to the cl-pd6833 or reducing the frequency of that clock. more power can be saved by putting the cl-pd6833 in the hw (hardware) suspend mode. to put the cl-pd6833 in the hw suspend mode, bit 4 of the miscellaneous control 3 (extended i/o index 25h) must be set to 1. thereafter, the led_out*/hw_suspend# pin can be driven to a 0 logic state. while in the hw suspend mode, the cl-pd6833 tristates all its outputs except the req# signal, which is driven high. during hw suspend mode, the pci bus signals to the cl-pd6833 can be turned off. however, the rst# signal on the pci bus must always be held high. an inactive state of the rst# signal ensures that the internal state of the cl-pd6833 is maintained during the power-down modes. table 3-4 illustrates the various power management modes and the corresponding power consumption. a the cl-pd6833 uses the clkrun mechanism to assert isa irqs. pci interrupts (inta# and/or intb#) and ri_out* can be asserted while the pci_clk is stopped. b the cl-pd6833 tristates all pci bus signals. req# is driven high on the pci bus. table 3-4. power consumption in various modes mode name rst# level measurement conditions typical power consumption normal operation high cl-pd6833 fully functional pci bus active core_vdd = 3.3 v pci_vcc,+5v = 5 v clock = 33 mhz tbd pci_clk stopped high only interrupts and ri_out* available a pci bus active core_vdd = 3.3 v pci_vcc,+5v = 5v clock = 0 mhz tbd hw suspend pci_clk stopped high only interrupts and ri_out* available a pci bus turned off b core_vdd = 3.3 v +5v = 5v pci_vcc = 0 v clock = 0 mhz tbd
june 1998 35 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.1.7 socket power management features 3.1.7.1 socket power control the cl-pd6833 provides two pins to serially control the socket power. these pins have multiple function- ality to allow the cl-pd6833 to interface with a number of socket power-control chips. following are the two socket power-control signalling modes supported by the cl-pd6833: l texas instruments tps2206aidf serial signalling mode l smbus ? ( system management bus) 1 signalling mode using the maxim 1601 the socket power-control signalling mode is usually established during power-on reset by the level of pins 131 (sdata/smbdata) and 130 (slatch/smbclk), but it can also be set by writing to bit 2 of the misc control 3 register. refer to table 3-5 for the con?guration of the power-control signalling mode. texas instruments tps2206aidf serial signalling mode in this mode, the cl-pd6833 can interface with the texas instruments tps2206aidf dual-socket pc card power interface switch, which uses a three-pin interface: sclk, sdata, and slatch (refer to figure 3-10 ). the pin sclk is connected to the 10C100-khz (usually 32-khz) clock typically available on the system. this serves as a reference clock for the cl-pd6833 and as a clock to the tps2206aidf. the data is serially transferred over sdata and the latch signal is slatch. figure 3-10. power control using texas instruments tps2206aidf serial signalling mode 1 smbus is a trademark of intel a corporation. table 3-5. socket power control con?guration socket power signalling mode slatch/smbclk (pin 130) misc control 3 bit 2 texas instruments tps2206aidf or external hardware serial mode pull-down 0 smbus (system management bus) pull-up 1 cl-pd6833 sdata/smbdata (131) slatch/smbclk (130) s data slatch sclk sclk sclk (132) tps2206aidf shdn# rst# s data slatch
advance data book v0.3 june 1998 36 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter external-hardware serial signalling mode in this mode, the cl-pd6701 is used to establish a parallel power-control interface (refer to figure 3-11 ). this mode enables the use of parallel socket power control chips. note: in the cl-pd6833, this mode is currently the same as texas instruments tps2206aidf serial signalling mode. figure 3-11. power control using external-hardware signalling mode system management bus signalling mode in this mode, the cl-pd6833 supports the intel a smbus (system management bus) protocol, which uses a two-pin interface: smbdata and smbclk (refer to figure 3-12 ). the system management bus is a sub- set of the i 2 c bus. the serial data is available on the smbdata pin and the serial clock is on the smbclk pin. the sclk pin is used as a reference clock for the cl-pd6833. the maxim max1601 dual-channel pc card v cc /v pp power-switching network supports the smbus protocol. the pci bus reset signal can be used to reset the max1601 chip. figure 3-12. power control using smbus signalling mode 3.1.7.2 card removal when a card is removed from a socket, the cl-pd6833 automatically disables the v cc and v pp supplies to the socket. the cl-pd6833 can also be con?gured to have management interrupts notify software of card removal. cl-pd6833 s data slatch sclk sclk cl-pd6701 reset# rst# - a_vcc_5 - a_vcc_3 a_vpp_vcc a_vpp_pgm - b_vcc_5 b_vpp_vcc b_vpp_pgm - b_vcc_3 sdata/smbdata (131) slatch/smbclk (130) sclk (132) s data slatch cl-pd6833 smbdata smbclk sclk max1601 vl rst# sdata/smbdata (131) slatch/smbclk (130) sclk (132)
june 1998 37 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.1.7.3 card insertion power to the socket is off at reset and whenever there is no card in a socket. when a card is detected (card detect input pins, cd1# and cd2#, to the cl-pd6833 become asserted low), power is applied by software after sensing card insertion. card insertion is sensed by allowing any change in state on the cd2# and cd1# pins to generate a management interrupt. 3.1.8 bus sizing the cl-pd6833 supports 32-bit transactions on the pci bus while supporting 8- or 16-bit pc cards. 3.1.9 programmable pc card timing the cl-pd6833 can be programmed to match the timing requirements of any pc card. the memory com- mand signals (we#, oe#) and i/o command signals (iowr#, iord#) at the pc card interface have three phases: setup, command, and recovery. these three phases are programmed by the timing registers on a per socket basis. there are two sets of timing registers, timer set 0 and timer set 1 , which can be selected on a per-window basis for both i/o and memory windows. 3.1.10 ata mode operation the cl-pd6833 supports direct connection to ata hard drives when in pc card 16 mode. ata drives use an interface very similar to the ide interface found on many popular portable computers. 3.1.11 pc card sensing the cl-pd6833 provides sensing capabilities for all types of cards and voltages compliant with the pc card speci?cation. this includes the following card types: l pc card 16 (r2) at 5.0 or 3.3 v l pc card 32 (cardbus) at 3.3 v the pins cd2#, cd1#, vs2, and vs1 are used to sense the types and operating voltages of inserted cards, as shown in table 3-6 . the x.x and y.y operating voltages are detected and re?ected in the present state register (memory offset 008h). values of these voltages are not yet de?ned by the pc card speci- ?cation.the cl-pd6833 assumes a low-voltage key (cardbus-capable socket in system). after pc card insertion, card type and voltage information is available in the socket present state register.
advance data book v0.3 june 1998 38 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.2 upgrading from the cl-pd6832 to the cl-pd6833 the cl-pd6833 is a direct pin replacement for the cl-pd6832. the cl-pd6833 has support for acpi and gpio pins to control the external buffers for zv (zoomed video) port. these features have to be con- sidered when designing a board that can accept the cl-pd6832 or the cl-pd6833 in the same footprint. table 3-7 depicts the essence of upgrading. the register bits in table 3-7 are part of the pme_cxt (pme context). they do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. the cl-pd6833 powers up in a default state with cl-pd6832 functionality. the only exception is pin 131. for acpi compliance, the board has to be designed so that during the period before powergood goes true, pin 131 is held low while pci_rst# is asserted low. during all other times, this pin behaves as sdata/smbdata output. the following example circuit can be used to provide the pci_rst# signal to pin 131 only when powergood is not true. when the powergood signal is not active, the fet table 3-6. card detect and voltage sense cd2#/ccd2# cd1#/ccd1# vs2/cvs2 vs1/cvs1 card type voltage (v) gnd gnd open open pc card 16 5.0 gnd gnd gnd gnd pc card 16 3.3/x.x gnd cvs1 open ccd1# pc card 32 3.3 cvs2 gnd ccd2# gnd pc card 32 3.3/x.x cvs1 gnd gnd ccd2# pc card 32 3.3/x.x/y.y gnd gnd gnd open pc card 16 x.x cvs2 gnd ccd2# open pc card 32 x.x gnd cvs2 ccd1# open pc card 32 x.x/y.y cvs1 gnd open ccd2# pc card 32 y.y gnd cvs1 gnd ccd1# reserved reserved gnd cvs2 ccd1# gnd reserved reserved table 3-7. upgrading from the cl-pd6832 to the cl-pd6833 pin number cl-pd6832Conly function cl-pd6833 function / bit values cl-pd6833 function / bit values register / bits 128 spkr_out* gpio3/01 914h / 5:4 133 ledout*/hw_suspend# pme#/10 gpio4/01 914h / 7:6 203 inta# led1* gpio1/01 914h / 1:0 204 intb#/ri_out* pme#/10 915h / 1:0 206 sin#/isdat led2* gpio2/01 914h / 3:2
june 1998 39 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter conducts and connects pci_rst# to pin 131. during this time, the cl-pd6833 internally ensures that pin 131 is an input. thereafter, when powergood is active, pins 131 and 207 are disconnected since the fet is not conducting. pin 131 can then become an output and drive either sdata or smbdata. figure 3-13. power-on detection for power management table 3-7 shows that after power-up, if registers 914h and 915h are programmed correctly, the cl-pd6833 provides the pme# signal for acpi compliance and/or provides the gpio signals for zv port buffers. as shown in table 3-7 , pme# is available either on pin 133 or pin 204. any illegal values (values other than the ones shown in table 3-7 ) programmed in these registers provide default cl-pd6832 pin functionality for the corresponding bits. additional features of the cl-pd6833 are: l in pci con?guration space, register 98h (see con?guration miscellaneous 1 on page 73 ) bit 2 enables the pci interrupts (inta#, intb#, ...) in the pci/way data stream. bit 8, when set to 1 locks registers 914h and 915h. bit 9, when set to 1 disables the read prefetch. bit 10, when set to 1 disables auto pc card reset during power state d3. this is a power saving feature. 3.2.1 added registers the following registers have been added to the pci con?guration space. note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. 3.2.1.1 pin multiplex control 0 register pme_cxt register name: pin multiplex control 0 register pci memory address: 914h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 led_out*/ hw_susp*/ pme#/gpio4 sel 1 led_out*/ hw_susp*/ pme#/gpio4 sel 0 spkr_out*/ gpio3/ sel 1 spkr_out*/ gpio3/ sel 0 sin#/isdat/ led2*/gpio2 sel 1 sin#/isdat/ led2*/gpio2 sel 0 inta#/led1*/ gpio1 sel 1 inta#/led1*/ gpio1 sel 0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 cl-pd6833 pin 131 pin 207 pci_rst# powergood
advance data book v0.3 june 1998 40 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter bits 1:0 pin 203 inta#/led1*/gpio1 pin function select bits 3:2 pin 206, sin#/isdat/led2*/gpio2 pin function select bits 5:4 pin 128, spkr_out*/gpio3 pin function select bits 7:6 pin 133, led_out*/hw_susp*/pme#/gpio4 pin function select a the socket a led indicator, active-low od, or led_out* if dual socket = 0. a the socket b led indicator, active-low od, or led_out* if con?gured for one led (dual socket = 0). bit 1 bit 0 pin function 0 0 inta# or led1* a 0 1 gpio1 1 0 do not program this value. 1 1 do not program this value. bit 3 bit 2 pin function 0 0 sin#, isdat, or led2* with control of pin characteristics per the cl-pd6832 bits. a 0 1 gpio2 1 0 do not program this value. 1 1 do not program this value. bit 5 bit 4 pin function 0 0 spkr_out* with control of pin characteristics per the cl-pd6832. 0 1 gpio3 1 0 do not program this value. 1 1 do not program this value. bit 7 bit 6 pin function 0 0 led_out* or hw_susp* with control of pin characteristics per the cl-pd6832. 0 1 gpio4 1 0 pme# as de?ned by pci speci?cation (pci power management add-on speci?cation). 1 1 do not program this value.
june 1998 41 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.2.1.2 pin multiplex control 1 register pme_cxt bits 1:0 pin 204, intb#/ri_out*/ pme# pin function select bits 7:2 reserved for future use register name: pin multiplex control 1 register pci memory address: 915h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfu intb#/ ri_out*/ pme# sel 1 intb#/ ri_out*/ pme# sel 0 r/w:0 r/w:0 r/w:0 bit 1 bit 0 pin function 0 0 intb# or ri_out*, using existing cl-pd6832 select bits. 0 1 do not program this value. 1 0 pme# as de?ned by pci speci?cation (pci power management add-on speci?cation). 1 1 do not program this value.
advance data book v0.3 june 1998 42 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter 3.3 host access to registers the cl-pd6833 cardbus registers can be accessed in memory-mapped mode only. other cl-pd6833 reg- isters can be accessed either in memory-mapped mode or i/o-mapped mode. to access registers in mem- ory-mapped mode, program the cl-pd6833 memory base address offset 10h in the con?guration space. to access registers in i/o-mapped mode, program offset 44h in the con?guration space accordingly. in i/o- mapped mode, the cl-pd6833 registers are accessed through an 8-bit indexing mechanism. an index reg- ister scheme allows a large number of internal registers to be accessed by the cpu using only two i/o addresses. the index register (see chapter 7, operation registers ) is used to specify which of the internal reg- isters the cpu accesses next. the value in the index register is called the register index and is the number that speci?es a unique internal register. the data register is used by the cpu to read and write the internal register speci?ed by the index register. figure 3-14. indexed 8-bit register structure figure 3-15. indexed 8-bit register example 00h 01h 02h ? ? 7eh 7fh ? internal registers register indexes i/o addresses data index low mid. byte low byte x x i/o i/o base address base address + 1 the following code segment demonstrates use of an indexed 8-bit register: mov dx, i/o_base_address mov al, 02h mov ah, 3ch out dx, ax 02h i/o i/o internal registers register indexes i/o addresses 3ch 02h 3ch x x base address base address + 1
june 1998 43 advance data book v0.3 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter the cl-pd6833 has extension registers that add to the functionality of the 82365sl-compatible register set. within the extension registers is an extended index register and extended data register that provide access to more registers. the registers accessed through extended index and extended data are thus double-indexed. the example below shows how to access the extension control 1 register, one of the dou- ble-indexed registers. ;write to extension control 1 register example ;constants section extended_index equ 2eh index_reg equ 2fh ext_cntrl_1 equ 03h i/o_base_addressequ xxx ;the base i/o address for the cl-pd6833 ;should be obtained through pci bios. ;code section mov dx, i/o_base_address mov al, extended_index mov ah, ext_cntrl_1 out dx, ax mov al, index_reg mov ah, user_data ;desired data to be out dx, ax ;written to ;extended index 03h ;read from extension control 1 register example ;code section mov dx, i/o_base_address mov al, extended_index mov ah, ext_cntrl_1 out dx, ax mov al, index_reg out dx, al inc dx ;al has extended in al, dx ;index 03h data
advance data book v0.3 june 1998 44 introduction to the cl-pd6833 cl-pd6833 pci-to-cardbus host adapter the following software code shows a sample of how to access the cl-pd6833 in memory-mapped mode. ; assume es selector points to base address ; 8-bit read access example mov ebx, 804h mov al, es:[bx] ; 16-bit read access example mov ax, es: [bx] ;32-bit read access example mov eax, es: [bx] ;8-bit write access example mov al, 6h mov es: [bx], al ; 16-bit write access example mov al, 0806h mov es: [bx], ax ; 32-bit write access example mov eax, 090a1206h mov es: [bx], eax 3.4 power-on setup following rst#-activated reset, the cl-pd6833 must be con?gured by host initialization or bios software. the application of the rst# signal on power-up causes initialization of all the cl-pd6833 register bits and ?elds to their reset values.
june 1998 45 advance data book v0.3 register description conventions cl-pd6833 pci-to-cardbus host adapter 4. register description conventions register headings the description of each register starts with a header containing the following information: special function bits following is a description of bits with special functions: a when the register is socket-speci?c, the index value given in the register heading is for socket a only. for the socket b register, add 40h to the index value of the socket a register to obtain the i/o address. the memory address of any socket register is an offset from the memory base address of the con?guration space for that socket. header field description register name this indicates the register name. offset this is added to the base address to generate the total effective address. register per this indicates whether the register affects both sockets, marked chip , or an individual socket, marked socket . if socket is indicated, there are two registers being described, each with a separate index value (one for each socket, a and b). a index a this is the index value through which an internal register in an indexed register set is accessed in i/o mode. register compatibility type this indicates whether the register is 82365sl-compatible, marked 365 ; a register extension, marked ext .; or dma-compatible for pci/way, marked dma . bit type description 0 or 1 these read-only bits are forced to either 0 or 1 at reset and cannot be changed. compatibility bit these bits have no function on the cl-pd6833, but are included for compatibility with the 82365sl register set. pci/way these bits provide the programming model for the pci/way dma support. pme_cxt (pme context) pme context is a set of bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. reserved these bits are reserved and should not be changed. scratchpad bit these read/write bits are available for use as bits of memory. sticky bit this is a read-only bit and must be cleared by writing a 1 to it. bit naming conventions the following keywords are used within bit and ?eld names: keyword description enable indicates that the function described in the rest of the bit name is active when the bit is 1. disable indicates that the function described in the rest of the bit name is active when the bit is 0. mode indicates that the bit alters the interpretation of the values in other registers. input indicates a bit or ?eld that is read from a pin. output indicates a bit or ?eld that is driven to a pin.
advance data book v0.3 june 1998 46 register description conventions cl-pd6833 pci-to-cardbus host adapter register bit types select indicates that the bit or ?eld selects between multiple alternatives. fields that contain select in their names have an indirect mapping between the value of the ?eld and the effect. status indicates one of two types of bits: either read-only bits used by the cl-pd6833 to report information to the system or bits set by the cl-pd6833 in response to an event that can also be cleared by the system. the system cannot directly cause a status bit to become 1. value indicates that the bit or ?eld value is used as a number. type description c clearable by writing a 1 to the bit r readable w writable bit naming conventions (cont.) the following keywords are used within bit and ?eld names: keyword description
june 1998 47 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5. pci configuration registers the cl-pd6833 has two pci con?guration register sets. each of these register sets corresponds to a socket. the second socket is the second function and starts at 100h. these register sets occupy con?g- uration offsets 00hC4fh. the register sets vary only in the function number (see pci bus speci?cation , rev. 2.1 for further information). they control basic pci bus functionality. pcmcia operation registers are accessed through either the memory base address register or the i/o base address register. the registers in this section are speci?c to each socket. table 5-1. pci con?guration registers quick reference register name memory offset page number vendor id and device id (device id = 1113h and vendor id = 1013h) 00h 48 command and status 04h 49 revision id and class code (revision id = 11100001 and class code = 060700h) 08h 52 cache line size, latency timer, header type, and bist (cache line size = 00h, header type = 82h, and bist = 0h) 0ch 53 memory base address 10h 54 cardbus status 14h 55 pci bus number, cardbus number, subordinate bus number, and cardbus latency timer 18h 57 memory base 0C1 1ch, 24h 58 memory limit 0C1 20h, 28h 59 i/o base 0C1 2ch, 34h 60 i/o limit 0C1 30h, 38h 61 interrupt line, interrupt pin, and bridge control 3ch 62 subsystem vendor id and subsystem device id 40h 65 pc card 16-bit if legacy mode base address 44h 66 reserved 48h7fh power management registers 80h 67 power management control and status 84h 68 dma slave con?guration register 90h 70 socket number 94h 71 con?guration miscellaneous 1 98h 73
advance data book v0.3 june 1998 48 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.1 vendor id and device id bits 15:0 vendor id this read-only ?eld is the vendor identi?cation assigned to cirrus logic by the pci special interest group. this ?eld always reads back 1013h. bits 31:16 device id this read-only ?eld is the device identi?cation assigned to this device by cirrus logic. this ?eld always reads back 1113h for the cl-pd6833. (revision number identi?cation for the cl-pd6833 part itself is indicated by the revision id ?eld in the revision id and class code register at con?guration offset 08h.) register name: vendor id and device id offset: 00h register per: chip bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 device id (high) device id (high) r:00010001 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 device id (low) device id (low) r:00010011 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 vendor id (high) vendor id (high) r:00010000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 vendor id (low) vendor id (low) r:00010011
june 1998 49 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.2 command and status bit 0 pci i/o space enable this bit does not affect r2 i/o space. bit 1 pci memory space enable this bit must be set for the cl-pd6833 to respond to memory transactions. this bit does not affect r2 memory space. bit 2 bus master enable this bit must be set to enable the bus master capability in the cl-pd6833. register name: command and status offset: 04h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 status (high) address/data parity error detected system error (serr#) generated received master abort received target abort signalled target abort devsel# timing master data parity error reported rc:0 rc:0 rc:0 rc:0 rc:0 r:01 rc:0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 status (low) fast back-to- back capable udf supported 66-mhz supported new capabilities present reserved r:0 r:0 r:0 r:1 r:0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 command (high) reserved system error (serr#) enable r:0000000 r/w:0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 command (low) wait cycle control parity error check/report enable reserved memory write and invalidate enable special cycle enable bus master enable pci memory space enable pci i/o space enable r:0 r/w:0 r:0 r:0 r:0 r/w:0 r/w:0 r/w:0 0 if this bit is 0 for both sockets a and b, any reads or writes to the i/o registers of the cl-pd6833 are ignored. if this bit is a 1, i/o accesses to the registers or cardbus card are carried out. for con?guration space 0, i/o accesses to both sockets are disabled. 1 the i/o space for the cl-pd6833 is enabled and responds to the reads and writes to the i/o address range de?ned in i/o base address register as well as any i/o window addresses. for con?guration space 0, this bit enables i/o register accesses for both sockets a and b. 0 the memory space for the cl-pd6833 is disabled. any reads or writes to the cl-pd6833 memory space are ignored. 1 the memory space for the cl-pd6833 is enabled, allowing access to memory window and memory- mapped cl-pd6833 registers. 0 bus master capability disabled. 1 bus master capability enabled.
advance data book v0.3 june 1998 50 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 3 special cycle enable this bit reads back a 0, since a pci-to-pci bridge cannot respond to special cycle transactions as a target. bit 4 memory write and invalidate enable this bit reads back a 0, since a pci-to-pci bridge cannot initiate a memory write and invalidate command. bit 5 reserved bit 6 parity error check/report enable this bit enables data parity-reporting-related circuitry, except for bit 31 of this register. bit 7 wait cycle control this bit always reads 0, indicating that the cl-pd6833 does not employ address or data stepping. bit 8 system error (serr#) enable this bit enables the cl-pd6833 to report system errors by asserting the serr# pin when address parity errors occur. bit 6 must also be set to 1 to allow a data parity error to cause serr# activation. see also the description of bit 30 in this register. bits 19:9 reserved bit 20 new capabilities present a 1 in this location indicates new capabilities in its con?guration space (cardbus controller and power management capabilities). the cardbus status register (offset 14h) is a pointer for these capabilities. it de?nes the locations of the registers described under the new capabilities function. bits 23:21 fast back-to-back capable, udf supported, and 66-mhz supported all of these features are not supported and read back 0s. bit 24 master data parity error reported this bit is set when a parity error is generated or detected, bit 6 of this register is set, and the cl-pd6833 is acting as a bus master. to clear this bit, software must write a 1 to it. bits 26:25 devsel# timing this ?eld always reads back 01, identifying the cl-pd6833 as a medium-speed device. bit 27 signalled target abort to clear this bit, software must write a 1 to it. 0 data parity checking and reporting is disabled. 1 data parity checking and reporting is enabled. 0 activation of serr# on address parity error is disabled. 1 serr# is activated whenever an address parity error is internally detected (slave mode). 0 no target device has signalled a target abort. 1 a target device has signalled a target abort.
june 1998 51 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 28 received target abort to clear this bit, software must write a 1 to it. bit 29 received master abort to clear this bit, software must write a 1 to it. bit 30 system error (serr#) generated this bit is set whenever the cl-pd6833 asserts serr# because of internal detection of a pci address parity error. bit 8 of this register must be set before system errors can be reported, and bit 6 must be set to allow address parity errors to be detected. the cl-pd6833 only asserts serr# if address parity errors occur. to clear this bit, software must write a 1 to it. bit 31 address/data parity error detected this bit indicates whether a parity error was detected, independent of whether bit 6 of this register is 1. to clear this bit, software must write a 1 to it. 0 no master transaction has been terminated with a target abort. 1 a master transaction has been terminated with a target abort. 0 no transaction has been terminated due to master abort. 1 a master device has terminated its transaction with master abort. 0 serr# was not asserted by this device. 1 serr# was asserted by this device, indicating a pci address parity error. 0 no data parity errors detected. 1 address or data parity error detected.
advance data book v0.3 june 1998 52 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.3 revision id and class code bits 7:0 revision id (11100001) this read-only ?eld identi?es the revision level of the cl-pd6833. it re?ects the value of bits 5:0 of the chip information register (index 1fh). bits 7 and 6 always read back a 1. note: having bits 4:0 as 0 indicates that the device id registers described in section 11.9 on page 159 should be used in determining revision id. bits 31:8 class code this ?eld always reads back 060700h, identifying the cl-pd6833 as a pcmcia/cardbus bridge device. a this read-only value depends on the revision level of the cl-pd6833. register name: revision id and class code offset: 08h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 class code (high) class code (high) r:00000110 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 class code (mid.) class code (mid.) r:00000111 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 class code (low) class code (low) r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 revision id 1 1 revision id r:1 r:1 r:nnnnnn a
june 1998 53 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.4 cache line size, latency timer, header type, and bist bits 7:0 cache line size this read-only ?eld is always 00h, indicating that the cl-pd6833 does not participate in pci- de?ned caching algorithms, and only generates memory write invalidate as a result of a pc card 32 master cycle. bits 15:8 latency timer 7:0 this ?eld programs the master latency time-out value. if the full byte is available, the latency timer programs in increments of one pci clock (pci_clk), but because bits 10:8 on the cl-pd6833 are read-only and must be programmed to 0h, master latency time-out values are programmable in increments of eight pci clocks. bits 23:16 header type this read-only ?eld is always 82h, specifying that the cl-pd6833 is a multi-function pci-to- cardbus bridge. bits 31:24 bist this read-only ?eld is reserved for bist information. if this ?eld returns all 0s on a read, then this device does not contain a bist. register name: cache line size, latency timer, header type, and bist offset: 0ch register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 bist bist r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 header type header type r:10000010 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 latency timer latency timer 7:3 latency timer 2:0 r/w:00000 r:000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 cache line size cache line size r:00000000
advance data book v0.3 june 1998 54 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.5 memory base address this is the pci memory address space base address for the operation registers. bit 0 memory space indicator this bit always reads back 0, indicating that this base address register de?nes a pci memory space. bits 2:1 type these bits indicate that the controller can be located anywhere in the 32-bit address space. bit 3 prefetchable this bit indicates that the controller registers are not prefetchable. bits 31:4 controller memory base address this ?eld speci?es the memory-mapped register space of the cl-pd6833. the operation registers can be accessed through this window only after these bits are set to a non-zero value. register name: memory base address offset: 10h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 controller memory base address (high) r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 controller memory base address (high mid.) r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 controller memory base address (low mid.) controller memory base address (low mid.) r/w:0000 r:0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 controller memory base address (low) prefetchable type memory space indicator r:0000 r:0 r:00 r:0
june 1998 55 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.6 cardbus status note: the cardbus (secondary) status bytes are similar to the status bytes in the command and status regis- ter, but contain information relating to the cardbus. bit 30 is de?ned differently than in the command and status register. these bits are reset by pci reset and by writing 1 to the bit. bits 7:0 power capabilities pointer this value indicates that the cardbus controller power management registers begin at offset 80h in this con?guration space. bits 23:8 reserved bit 24 secondary bus data parity error reported this bit is used to report the receipt of perr# on the pc card 32 bus. write a 1 to this bit to clear it. bits 26:25 reserved bit 27 signalled target abort to clear this bit, software must write a 1 to it. bit 28 received target abort to clear this bit, software must write a 1 to it. register name: cardbus status offset: 14h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 cardbus status (high) address/data parity error detected received system error (serr#) received master abort received target abort signalled target abort reserved secondary bus data parity error reported rc:0 rc:0 rc:0 rc:0 rc:0 r:00 rc:0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 cardbus status (low) reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 power capabilities pointer r:10000000 0 no target device has signalled a target abort. 1 a target device has signalled a target abort. 0 no master transaction has been terminated with a target abort. 1 a master transaction has been terminated with a target abort.
advance data book v0.3 june 1998 56 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 29 received master abort to clear this bit, software must write a 1 to it. bit 30 received system error (serr#) this bit is set whenever the cardbus interface detects an address parity error. bit 17 of the interrupt line, interrupt pin, and bridge control register (memory offset 3ch) must be set before system errors can be reported, and bit 16 of the interrupt line, interrupt pin, and bridge control register must be set to allow address parity errors to be detected. the cl-pd6833 only asserts serr# if address parity errors occur. to clear this bit, software must write a 1 to it. bit 31 address/data parity error detected this bit indicates whether a parity error was detected, independent of whether bit 16 of the bridge control register (memory offset 3ch) is 1. to clear this bit, software must write a 1 to it. 0 no transaction has been terminated due to master abort. 1 a master device has terminated its transaction with master abort. 0 serr# assertion on the cardbus interface has not been detected. 1 serr# assertion on the cardbus interface has been detected. 0 no data parity errors detected. 1 address or data parity error detected.
june 1998 57 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.7 pci bus number, cardbus number, subordinate bus number, and cardbus latency timer bits 7:0 pci bus number this byte identi?es the number of the pci bus on the primary side of the bridge. this byte is set by pci bios con?guration software. bits 15:8 cardbus number this byte identi?es the number of the cardbus attached to the socket, and it is set by pci bios con?guration software or socket services. bits 23:16 subordinate bus number this byte is de?ned for pci-to-pci bridges. it identi?es the number of the bus at the lowest part of the hierarchy behind the bridge. normally, a cardbus bridge is at the bottom of the bus hierarchy and this register holds the same value as the cardbus number register. bits 31:24 cardbus latency timer 7:0 this byte has the same functionality as the primary pci bus latency timer, but applies to the cardbus attached to this speci?c socket. this byte is set by pci bios con?guration software or socket services. register name: pci bus number, cardbus number, subordinate bus number, and cardbus latency timer offset: 18h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 cardbus latency timer cardbus latency timer 7:3 cardbus latency timer 2:0 r/w:00000 r:000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 subordinate bus number subordinate bus number r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 cardbus number cardbus number r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 pci bus number pci bus number r/w:00000000
advance data book v0.3 june 1998 58 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.8 memory base 0C1 note: memory base 0C1 and memory limit 0C1 are enabled by bit 1 of the command and status register (memory offset 04h). to disable one window, set bits 31:12 to the limit of that window equal to or below the corresponding base address. bits 31:0 memory base 31:0 this register de?nes the bottom address of a pci memory window to be mapped to cardbus- capable pc card memory space. the upper 20 bits correspond to pci address bits ad[31:12]. the bottom 12 bits (which correspond to pci address bits ad[11:0]) of this register are read-only and return 0 when read. register name: memory base 0C1 offset: 1ch, 24h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 memory base 31:24 r/w:11111111 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 memory base 23:16 r/w:11111111 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 memory base 15:12 memory base 11:8 r/w:1111 r:0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 memory base 7:0 r:00000000
june 1998 59 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.9 memory limit 0C1 note: memory base 0C1 and memory limit 0C1 are enabled by bit 1 of the command and status register (memory offset 04h). to disable one window, set bits 31:12 to the limit of that window equal to or below the corresponding base address. bits 31:0 memory limit 31:0 this register de?nes the top address of a pci memory window to be mapped to cardbus-capable pc card memory space. the upper 20 bits correspond to pci address bits ad[31:12]. the bottom 12 bits (which correspond to pci address bits ad[11:0]) are read-only and return 0 when read; however, the bridge assumes pci address bits ad[11:0] are 1s to determine the range de?ned, so if memory base 0C1 and memory limit 0C1 registers are set to the same value, a 4-kbyte window is de?ned. register name: memory limit 0C1 offset: 20h, 28h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 memory limit 31:24 r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 memory limit 23:16 r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 memory limit 15:12 memory limit 11:8 r/w:0000 r:0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 memory limit 7:0 r:00000000
advance data book v0.3 june 1998 60 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.10 i/o base 0C1 bits 1:0 i/o space indicator 1:0 these bits are an extension to the i/o base register and always read back 00. the value 00 indicates that the cl-pd6833 supports 16-bit pci i/o address decoding. as described in the pci-to-cardbus register description speci?cation , this means i/o access intended for cardbus cards require pci address bits 31:16 to be 0. bits 15:2 i/o base 15:2 these bits de?ne the bottom of an address range of a pci i/o window to be mapped to a cardbus- capable pci i/o space. these bits correspond to pci i/o address bits 15:2. bits 31:16 i/o base 31:16 these bits read all 0s to be compatible with the cl-pd6832. note: i/o base 0C1 and i/o limit 0C1 registers are enabled by bit 0 of the command and status register. to disable one window, set the limit of that window below the base. for example, if i/o base is equal to i/o limit, the cl-pd6833 does doubleword i/o addressing. register name: i/o base 0C1 offset: 2ch, 34h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 i/o base 31:24 r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 i/o base 23:16 r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 i/o base 15:8 r/w:11111111 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 i/o base 7:2 i/o space indicator r/w:111111 r:00
june 1998 61 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.11 i/o limit 0C1 bits 1:0 reserved these bits are reserved and always read back 00. bits 15:2 i/o limit 15:2 these bits de?ne the top of an address range of a pci i/o window to be mapped to a cardbus- capable pci i/o space. these bits correspond to pci i/o address bits 15:2. bits 31:16 i/o limit 31:16 these bits read all 0s to be compatible with the cl-pd6832. register name: i/o limit 0C1 offset: 30h, 38h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 i/o limit 31:24 r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 i/o limit 23:16 r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 i/o limit 15:8 r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 i/o limit 7:2 reserved r/w:000000 r:00
advance data book v0.3 june 1998 62 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.12 interrupt line, interrupt pin, and bridge control bits 7:0 interrupt line this register is used by software to communicate the routing of the interrupts (inta# for socket a and intb# for socket b). bits 15:8 interrupt pin these read-only registers indicate that the cl-pd6833 requires one interrupt line per function (socket a and socket b) and that these lines are inta# and intb#. bit 16 cardbus parity error response enable this bit determines the response to parity errors on the cardbus interface. bit 17 cardbus system error (serr#) enable this bit controls the forwarding of the cardbus interface serr# assertions to the primary interface. bit 18 isa enable this bit is not implemented. register name: interrupt line, interrupt pin, and bridge control offset: 3ch register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 bridge control (high) reserved write posting enable memory 1 prefetch enable memory 0 prefetch enable r:00000 r/w:0 r:0 r:0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 bridge control (low) ireq-int enable cardbus reset master abort mode reserved vga enable isa enable cardbus system error (serr#) enable cardbus parity error response enable r/w:0 r/w:1 r/w:0 r:0 r:0 r:0 r/w:0 r/w:0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 interrupt pin interrupt pin r:00000001/00000010 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 interrupt line interrupt line r/w:00000000 0 ignore address/data parity errors on the cardbus interface. 1 enable parity error reporting and detection on the cardbus interface. 0 disable forwarding of cardbus interface serr# to the primary interface. 1 enable forwarding of cardbus interface serr# to the primary interface.
june 1998 63 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 19 vga enable this bit is not implemented. bit 20 reserved bit 21 master abort mode this bit controls the behavior of the bridge when a master abort termination occurs on either interface while bridge is the master. bit 22 cardbus reset this bit forces a reset on the cardbus interface whenever it is set. the cardbus interface is also reset whenever the rst# of the primary interface is asserted. note that when the crst# pin on the cardbus interface is asserted (low), this does not mean the primary interface gets reset too. forcing a reset on the cardbus interface causes its con?guration registers to reset to their default states. bit 23 ireq-int enable this bit is used to control the routing of pc card ireq (or cireq for cardbus cards) interrupts to isa irq or pci int pin. this is used only when the cl-pd6833 is programmed for non-pci style interrupts. when this bit is set to 1, pc card ireq (cireq) interrupts are routed to the isa irq line (irq3, 4, 5, 7, 11, 12, 14, or 15) as indicated by the interrupt and general control register (memory offset 803h). when this bit is set to 0, pc card ireq (cireq) interrupts are routed to the int pin indicated by the interrupt pin register (memory offset 3dh): inta# for socket a and intb# for socket b. if the cl-pd6833 is programmed for ring indicate, then intb# is used for ring out and inta# is used for both sockets a and b, that is, intb# is not available for function interrupt routing. bit 24 memory 0 prefetch enable this bit is not implemented. bit 25 memory 1 prefetch enable this bit is not implemented. 0 do not report master aborts and return all ones (ffffffffh) on reads and discard data on writes to the secondary master. 1 report master aborts by signalling target abort, if possible, or by asserting serr# if enabled. 0 the reset signal to the cardbus card is inactive (high). 1 the reset signal to the cardbus card is active (low). 0 pc card interrupts are routed to the intx# pin indicated by the interrupt pin register. 1 pc card interrupts are routed to the isa irq pin indicated by the interrupt and general control register. 0 read prefetching for memory window 0 is disabled. 1 read prefetching for memory window 0 is enabled. 0 read prefetching for memory window 1 is disabled. 1 read prefetching for memory window 0 is enabled.
advance data book v0.3 june 1998 64 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 26 write posting enable this bit enables posting of write data to the socket. if this bit is not set, the bridge must drain any data in its buffers before accepting data for the socket. each data word must then be accepted by the target before the bridge can accept the next one from the source master. the bridge must not release the source master until the last word is accepted by the target. operating with write posting disabled inhibits system performance. bits 31:27 reserved 0 write posting is disabled. 1 write posting is enabled.
june 1998 65 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.13 subsystem vendor id and subsystem device id bits 15:0 subsystem vendor id this ?eld is the identi?cation assigned to the subsystem vendor by the pci special interest group. it must be set by the software. bits 31:16 subsystem device id this ?eld is the device identi?cation assigned by the subsystem vendor to its device. it must be set by the software. notes: 1) after writing to this register, set the subsystem vendor id lock bit (register 98h, bit 0) to 0. 2) if the subsystem vendor id lock bit is set, this register becomes read only and cannot be written to. register name: subsystem vendor id and subsystem device id offset: 40h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 subsystem device id (high) subsystem device id (high) r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 subsystem device id (low) subsystem device id (low) r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 subsystem vendor id (high) subsystem vendor id (high) r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 subsystem vendor id (low) subsystem vendor id (low) r/w:00000000
advance data book v0.3 june 1998 66 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.14 pc card 16-bit if legacy mode base address this is the pci i/o space base address for the operation registers. bits 1:0 i/o space indicator these bits always read back 01, indicating that this base address register de?nes a pci i/o space. bits 31:2 controller i/o base address this ?eld speci?es the i/o-mapped register space of the cl-pd6833. the operation registers can be accessed through this window only after these bits are set to a non-zero value. the allowable range is anywhere in the i/o map. for legacy software, this register should be set to 000003e1h. register name: pc card 16-bit if legacy mode base address offset: 44h register per: chip bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 controller i/o base address (high) r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 controller i/o base address (high mid.) r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 controller i/o base address (low mid.) r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 controller i/o base address (low) i/o space indicator r/w:000000 r:01
june 1998 67 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.15 power management registers bits 7:0 capabilities id this register identi?es the rest of the registers in this section as a power management structure. bits 15:8 next item pointer this register indicates that this section is the last of the capabilities structures. bits 18:16 pci power management revision the value 001 indicates that the cl-pd6833 complies with version 1.0 of the pci power management interface speci?cation . bits 31:19 power management capabilities these bits indicate the following: pme# can be asserted in power management state d0, d1, d2, and d3 sw . this device supports power management state d1 and d2. this device does not require a full speed clock to operate. this bridge is capable of dynamic clock control and supports the clk_run# protocol. this device does not require device speci?c software prior to use. this device is compliant with version 1.0 of the pci power management interface speci?cation . register name: power management registers offset: 80h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 pme# from d3 cold pme# from d3 hot pme# from d2 pme# from d1 pme# from d0 d2 support d1 support dynamic data support r:1 r:1 r:1 r:1 r:1 r:1 r:1 r:0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved device specific initialization aux power source pme clock pci power management revision r:0 r:0 r:1 r:0 r:001 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 next item pointer r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 capabilities id r:00000001
advance data book v0.3 june 1998 68 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.16 power management control and status bits 1:0 power state these two bits de?ne the acpi-de?ned power state of the socket interface. bits 7:2 reserved bit 8 pme enable (pme_en) this bit enables the wake-up function of the cl-pd6833. when this bit is set, wake-ups are signalled on the pme pin. when this bit is reset, no wake-ups are issued. bits 12:9 data select these bits read back 0s to indicate that data selection is not supported. bits 14:13 data scale these bits read back 0s to indicate that data readback is not supported. register name: power management control and status offset: 84h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 data r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 bpcc_en b2_b3# reserved r:0 r:0 r:000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 pme status data scale data select pme enable (pme_en) r/w:sticky r:00 r:0000 r/w:sticky bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reserved power state r:000000 r/w:00 bit 1 bit 0 power state of socket interface 00 d0 01 d1 10 d2 11 d3
june 1998 69 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 15 pme status this bit indicates that an event has occurred that, if the pme enable bit is set, would cause pme to be signalled. writing a 1 to this bit clears it to 0, and writing 0 to this bit has no effect. bits 21:16 reserved bit 22 b2_b3# (b2/b3 support for d3 hot ) this bit set to 0 and is not meaningful because bit 23 (bpcc_en) is set to 0. bit 23 bpcc_en (bus power / clock control enable) this bit is set to 0. a 0 indicates that the bus power/clock control policies have been disabled. note: bits 23:16 always read back 0s to indicate that the data register is not supported. bits 31:24 data
advance data book v0.3 june 1998 70 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.17 dma slave con?guration register this is the dma i/o base address for the dma registers. bit 0 channel enable this bit, along with the dreq enable bits in extension control 1, enables the dma channel. when this bit is 0, dma operations are not allowed. if both of the dreq enable bits in extension control 1 are 0s, dma operations are not allowed. bits 2:1 transfer size these bits de?ne the size of the dma transfer at the pc card 16 (r2) socket. bit 3 non-legacy extended addressing when this bit is set to 1, it enables use of the dma extended addressing. bits 31:4 dma i/o base address these bits are used to de?ne the i/o address where the dma operation registers can be located. a these two settings are implemented for compatibility with current r2 conventions. register name: dma slave configuration register offset: 90h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 dma i/o base address (high) r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 dma i/o base address (high mid.) r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 dma i/o base address (low mid.) r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 dma i/o base address (low) non-legacy extended addressing transfer size channel enable r/w:0000 r/w:0 r/w:00 r/w:0 bit 2 bit 1 size of dma transfer at the pc card 16 (r2) socket 0 0 8-bit transfer at the pc card 0 1 16-bit transfers at the pc card 1 0 16-bit transfers at the pc card a 1 1 16-bit transfers at the pc card a
june 1998 71 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.18 socket number this is the socket number used for backward-compatible addressing in the i/o space. bits 2:0 socket number these bits de?ne the socket number that is used for the i/o addressing mode of operation. sockets a and b must have the same address, and therefore bit 2 of this register must be the same for each con?guration space. for software compatibility with earlier cl-pd67xx pc card host adapters, many of the cl-pd6833 internal registers are accessible at the i/o address pair 03e0h and 03e1h by setting a register index at one address, and then accessing the 8-bit register data at the next address. register name: socket number offset: 94h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reserved socket number r:00000 r/w:000 / 001 bit 2 bit 1 bit 0 socket number index range example pci i/o address (if pci i/o base address is programmed to 03e0) 0000 00h3fh index register at 03e0, data at 03e1 0011 40h7fh index register at 03e0, data at 03e1 0102 80hbfh index register at 03e0, data at 03e1 0113c0h ffh index register at 03e0, data at 03e1 1004 00h3fh index register at 03e2, data at 03e3 1015 40h7fh index register at 03e2, data at 03e3 1106 80hbfh index register at 03e2, data at 03e3 1117c0h ffh index register at 03e2, data at 03e3
advance data book v0.3 june 1998 72 pci configuration registers cl-pd6833 pci-to-cardbus host adapter with this organization, bits 7:6 of the index value are used to select access to socket a or socket b registers. in an isa environment, bits 7:6 of the index value can also be used to select one of four sockets when two pc card host adapters are paired in a system. some older pc card host adapters also allow setting of its older address pair to 03e2h and 03e3h instead of the default 03e0h and 03e1h. this could allow up to eight sockets to be supported in a system: four at the i/o address pair 03e0/03e1h and four at the i/o address pair 03e2/03e3h. bits 2:0 of this register can be used to map i/o space-accessible internal registers for a socket into an i/o address pair and index range so that it appears as a particular socket number out of the eight possible socket number locations found in older isa-based pc card host adapters. refer to chapter 7 for information about the organization of the index register. bits 31:3 reserved
june 1998 73 advance data book v0.3 pci configuration registers cl-pd6833 pci-to-cardbus host adapter 5.19 con?guration miscellaneous 1 bit 0 subsystem vendor id lock this bit defaults to 0. when this bit is set to 1, the subsystem vendor id and subsystem device id registers (memory offset 40h) become read only. this register is per chip. bit 1 management enable this bit is used to control the routing of management interrupts to the isa irq or pci int pin. this is used only when the cl-pd6833 is programmed for non-pci style interrupts. bit 2 enable inta#, intb# in pci/way this register is per chip. bits 7:3 reserved bit 8 pin mapping lock this bit determines the pci memory space 914hC915h pin mapping register accessibility. (bit position is r/w for each socket: chip-level function, programmable in function 0 only.) register name: configuration miscellaneous 1 offset: 98h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved d3 disable auto reset pme_cxt disable master prefetch pin mapping lock r:000000 r/w:0 r/w:0 r/w:0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reserved enable inta#, intb# in pci/way management enable subsystem vendor id lock r:00000 r/w:0 r/w:0 r/w:0 0 management interrupts are routed to the int pin indicated by the interrupt pin register (memory offset 3dh): inta# for socket a and intb# for socket b. 1 management interrupts are routed to the isa irq line (irq3, 4, 5, 7, 11, 12, 14, or 15) as indicated by the management interrupt con?guration register (memory offset 805h). 0 pci/way data stream is compatible with the cl-pd6832. 1 inta# and intb# are included in the pci/way data stream. 0 pin mapping can be programmed in register 914C915h. 1 write access to register 914C915h is disabled.
advance data book v0.3 june 1998 74 pci configuration registers cl-pd6833 pci-to-cardbus host adapter bit 9 disable master prefetch this bit determines the cardbus master prefetch behavior. (bit position is r/w for each socket: chip-level function, programmable in function 0 only.) bit 10 d3 disable auto reset pme_cxt this bit determines the cl-pd6833 action when the sockets pci function is in d3 power state. this bit is part of the pme_cxt, a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 31:11 reserved 0 cardbus master prefetching from pci memory is allowed. 1 cardbus master prefetching from pci is disabled. 0 reset signal to cards is activated in d3 if card is powered. 1 automatic card reset in d3 is disabled.
june 1998 75 advance data book v0.3 cardbus registers cl-pd6833 pci-to-cardbus host adapter 6. cardbus registers the cardbus registers occupy offsets 000hC7ffh from the memory base address register. these registers are reset by rst#. 6.1 status event pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. the status event register indicates when a change in socket status occurs. these bits do not indicate what the change is, only that a change occurred. software must read the present state register for cur- rent status. bits 3:0 can be cleared by writing a 1 to each bit. these bits can be set to 1 by software through writing 1 to the corresponding bit in the event force register, provided the status mask register has been set. all bits in this register are cleared by rst#. software needs to clear this register before enabling interrupts. table 6-1. cardbus registers quick reference register name memory offset page number status event pme_cxt 000h 75 status mask pme_cxt 004h 77 present state 008h 78 event force 00ch 80 control pme_cxt 010h 82 register name: status event pme_cxt memory offset: 000h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reserved power cycle ccd2 ccd1 cstschg/ wakeup r:0000 r/c:0 r/c:0 r/c:0 r/c:0
advance data book v0.3 june 1998 76 cardbus registers cl-pd6833 pci-to-cardbus host adapter bit 0 cstschg/wakeup (card status change and/or wakeup) this bit indicates that the cstschg and/or wakeup signal has been asserted. it only indicates the assertion event. it is not a re?ection of the cstschg bit from the card. it is latched by the controller and must be explicitly cleared by the appropriate software. the status change interrupt, driven by the controller, must be based on this event bit rather than the present value register. when a card is powered, this bit indicates a status change and is driven continuously by the card. when a socket is powered down, this bit is a wakeup bit. a card might only drive it for 1 ms to limit drain on a battery. to be used in this manner, a card must have an external supply or battery. deassertion of cstschg is controlled by software or a reset clearing the signal on the bus. indicating that change would not be useful. this bit is not set if an event is detected during the time period when the cl-pd6833 has started the power-up cycle of the socket, but has not yet signalled a power up complete interrupt. this prevents spurious signals from a card during power-up, generating invalid events. this bit is re- enabled when the power complete interrupt is generated. during the power down sequence, the card is responsible for preventing glitches. bit 1 ccd1 this bit indicates a change has occurred in the corresponding card detect bit. bit 2 ccd2 this bit indicates a change has occurred in the corresponding card detect bit. bit 3 power cycle this bit defaults to 0. it is set to 1 by the cl-pd6833 to indicate that the device has completed powering up or powering down. the present state register (memory offset 008h) should be read to determine that the voltage requested is actually applied. the cl-pd6833 does not allow an unsupported voltage to be applied to a pc card 32 (cardbus) card. this bit is meaningless when a 16-bit card is in the socket. it is not possible to power up a pc card 32 (cardbus) card to a voltage not indicated by the vs/cd lines. bits 31:4 reserved
june 1998 77 advance data book v0.3 cardbus registers cl-pd6833 pci-to-cardbus host adapter 6.2 status mask pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 by a software pci bus segment reset. this register gives software the ability to control the events that can cause interrupts. if the card detect changed bit is enabled at the time a card is removed, an interrupt is generated. this register is cleared automatically when card is removed. if the cl-pd6833 is required to generate an interrupt when a new card is inserted, software must again set the card detect changed mask bit. bit 0 cstschg/wakeup (card status change / wakeup) when set, this bit enables an interrupt based on the cstschg signal being asserted by a cardbus card. cstschg interrupts generated by 16-bit cards are controlled by registers in that interfaces register space. this bit is disabled when it is 0. bit 1 ccd1 changed when set, this bit enables an interrupt when the cl-pd6833 detects change. bit 2 ccd2 changed when set, this bit enables an interrupt when the cl-pd6833 detects change. bit 3 power cycle complete when set, this bit causes the cl-pd6833 to generate an interrupt 256 cycles of the pci clock after powering up a socket. bits 31:4 reserved register name: status mask pme_cxt memory offset: 004h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reserved power cycle complete ccd2 changed ccd1 changed cstschg/ wakeup r:0000 r/w:0 r/w:0 r/w:0 r/w:0
advance data book v0.3 june 1998 78 cardbus registers cl-pd6833 pci-to-cardbus host adapter 6.3 present state the socket present state register re?ects the present value of the socket status. some of the bits in this register are merely re?ections of interface signals, while others are ?ags set to indicate a status change. bit 0 cstschg/wakeup this bit re?ects the current status of the cstschg/wakeup pin on the cardbus interface. bit 1 ccd1 this bit provides for detection of a pc card insertion/removal/presence. it is also used by the cl-pd6833, in conjunction with cvs1, to determine the card type (pc card 16 vs. pc card 32). it is a re?ection of the ccd1 pin. bit 2 ccd2 this bit provides for detection of a pc card insertion/removal/presence. it is also used by the cl-pd6833, in conjunction with cvs2, to determine the card type (pc card 16 vs. pc card 32). it is a re?ection of the ccd2 pin. bit 3 power cycle complete when this bit is set, it indicates that the interface is powered up. when this bit is cleared, the socket is powered down. this bit is set to 0 by pcirst#. bit 4 16-bit pc card when this bit is set, it indicates that the card detect state machine determined a pc card 16 (r2) card was inserted. this bit is cleared when another card, one that is not 16-bit, is inserted. this bit is set to 0 by pcirst#. a ru indicates a read update. register name: present state memory offset: 008h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 y-v socket x-v socket 3.3-v socket 5-v socket reserved ru a r:0 ru a r:0 ru a r:1 ru a r:1 r:0000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved y-v card x-v card 3.3-v card 5-v card bad v cc request data lost r:00 ru a r:0 ru a r:0 ru a r:0 ru a r:0 ru a r:0 r rc:0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 not a card interrupt cardbus pc card 16-bit pc card power cycle complete ccd2 ccd1 cstschg/ wakeup ru a r:0 ru a r:0 ru a r:0 ru a r:0 ru a r:0 ru a r:1 ru a r:1 ru a r:0
june 1998 79 advance data book v0.3 cardbus registers cl-pd6833 pci-to-cardbus host adapter bit 5 cardbus pc card when this bit is set, it indicates that the card detect state machine determined a pc card 32 (cardbus) card was inserted. this bit is cleared when another card, one that is not cardbus, is inserted. this bit is set to 0 by rst#. note: this bit and the 16-bit pc card bit do not indicate that a card is installed. they only indicate what kind of card was last installed. the card detect bits indicate if a card is currently in the socket. bit 6 interrupt when this bit is set to 1, it indicates that the inserted card is driving its interrupt pin active. this bit is not registered and its assertion/deassertion follows the interrupt pin from the card. bit 7 not a card this bit indicates that an unsupported card is installed in the socket. the cl-pd6833 does not allow power to be applied to the socket if this bit is set. this bit is set to 0 by rst#. bit 8 data lost this bit indicates that a card was removed while the interface was active. data may be lost. any data in the cl-pd6833 data buffers is lost when this event occurs. this bit is set to 0 by rst#. this bit allows software to fail in a graceful manner, if it chooses to, when this occurs. bit 9 bad v cc request this bit indicates that software attempted to apply an unsupported or incorrect voltage level to a pc card 32 (cardbus) card. this bit is set to 0 by rst#. bit 10 5-v card when this bit is set, the card installed requires and/or supports 5.0-v operation. this bit is set by the state machine used to detect card voltage requirements. this bit is set to 0 by rst#. bit 11 3.3-v card when this bit is set, the card installed requires and/or supports 3.3-v operation. this bit is set by the state machine used to detect card voltage requirements. this bit is set to 0 by rst#. bit 12 x-v card when this bit is set, the card installed requires and/or supports x-v operation. this bit is set by the state machine used to detect card voltage requirements. this bit is set to 0 by rst#. bit 13 y-v card when this bit is set, the card installed requires and/or supports y-v operation. this bit is set by the state machine used to detect card voltage requirements. this bit is set to 0 by rst#. bits 27:14 reserved bits 31:28 socket voltage availability these bits indicate the v cc voltages available for the sockets in this system. 31 30 29 28 y v x v 3.3 v 5.0 v
advance data book v0.3 june 1998 80 cardbus registers cl-pd6833 pci-to-cardbus host adapter 6.4 event force the event force register is a phantom register. these bits are merely control bits. they are not registered and need no clearing. they provide software the ability to force various status and event bits in the cl-pd6833. this gives software the ability to test and restore status. writing 1 to a bit in this register sets the corresponding bit in the status event register and/or the present state register. bits 3:0 generate management interrupt if the correct mask bit is set. bit 0 cstschg/wakeup this bit sets the card status change bit in the status event register. the present state register remains unchanged. bit 1 ccd1 changed this bit sets the ccd1 bit in the status event register. the present state register remains unchanged. bit 2 ccd2 changed this bit sets the ccd2 bit in the status event register. the present state register remains unchanged. bit 3 power cycle this bit sets the power cycle bit in the status event register. the present state register remains unchanged. bit 4 16-bit pc card this bit sets the 16-bit pc card bit in the present state register. if a card is installed in the socket, writes to this bit are ignored. register name: event force memory offset: 00ch register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved cv test y-v x-v 3.3-v card 5-v card bad v cc request data lost w:0 w:0 w:0 w:0 w:0 w:0 w:0 w:0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 not a card reserved cardbus pc card 16-bit pc card power cycle ccd2 changed ccd1 changed cstschg/ wakeup w:0 w:0 w:0 w:0 w:0 w:0 w:0 w:0
june 1998 81 advance data book v0.3 cardbus registers cl-pd6833 pci-to-cardbus host adapter bit 5 cardbus pc card this bit sets the cardbus pc card bit in the present state register. if a card is installed in the socket, writes to this bit are ignored. bit 7 not a card this bit sets the not a card bit in the present state register. if a card is installed in the socket, writes to this bit are ignored. bit 8 data lost this bit causes the data lost bit to be set in the present state register. bit 9 bad v cc request this bit causes the bad v cc request bit in the present state register to be set. bit 10 5-v card this bit causes the 5-v card bit in the present state register to be set. writes to this bit disable the cl-pd6833s ability to power up the socket. to change the voltage of a card, after forcing this bit, the cl-pd6833 must either receive a rst# or retest the cards supported voltages. the latter can be accomplished by forcing the cv test bit (bit 14 in this register). this is necessary to prevent software from applying an incorrect voltage to the pc card. bit 11 3.3-v card this bit causes the 3.3-v card bit in the present state register to be set. writes to this bit disables the cl-pd6833s ability to power up the socket. to change the voltage of a card, after forcing this bit, the cl-pd6833 must either receive a rst# or retest the cards supported voltages. the latter can be accomplished by forcing the cv test bit (bit 14 in this register). this is necessary to prevent software from applying an incorrect voltage to the pc card. bit 12 x-v card this bit causes the x-v card bit in the present state register to be set. writes to this bit disables the cl-pd6833s ability to power up the socket. to change the voltage of a card, after forcing this bit, the cl-pd6833 must either receive a rst# or retest the cards supported voltages. the latter can be accomplished by forcing the cv test bit (bit 14 in this register). this is necessary to prevent software from applying an incorrect voltage to the pc card. bit 13 y-v card this bit causes the y-v card bit in the present state register to be set. writes to this bit disables the cl-pd6833s ability to power up the socket. to change the voltage of a card, after forcing this bit, the cl-pd6833 must either receive a rst# or retest the cards supported voltages. the latter can be accomplished by forcing the cv test bit (bit 14 in this register). this is necessary to prevent software from applying an incorrect voltage to the pc card. bit 14 cv test this bit causes the controller to test the vs and ccd lines to determine card type and voltages supported. this test is run automatically when a new card is inserted. bits 31:15 reserved
advance data book v0.3 june 1998 82 cardbus registers cl-pd6833 pci-to-cardbus host adapter 6.5 control pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 by a software pci bus segment reset. the socket control register provides control of the sockets v cc and v pp . all bits in this register are set to 0 by rst# and power removed from the socket. this register is write-protected by writes to bits 13:10 of the event force register, and not write-protected on completion of the decoding sequence of the cd1, cd2, vs1, and vs2 lines or completion of cv test. use either this register or the power control register (index 02h) for power control. do not use both registers. bits 2:0 v pp control these bits are used to switch the v pp power using external v pp control logic. the cl-pd6833 has no knowledge of a cards v pp voltage requirement. software must determine the needed voltage from the cards cis. the following table shows the v pp requested depending on the setting of the bits. register name: control pme_cxt memory offset: 010h register per: socket bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 reserved r:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 reserved r:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 reserved r:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 stop clock v cc control reserved v pp control r/w:0 r/w:000 r:0 r/w:000 bit 2 bit 1 bit 0 v pp requested 000 0 v 0 0 1 12.0 v 0 1 0 5.0 v 0 1 1 3.3 v 100111 reserved
june 1998 83 advance data book v0.3 cardbus registers cl-pd6833 pci-to-cardbus host adapter bits 6:4 v cc control these bits are used to control the power to the pc card using external control logic. the cl-pd6833 determines the voltages that can be applied by decoding the cd and vs signals according to the cardbus speci?cation , which are re?ected in the present state register. the settings in the present state register that determine the voltages available in the system determine the v cc options. the value written to this register must agree with the value needed to apply the correct value of v cc . the cl-pd6833 must not allow an incorrect v cc voltage to be applied to a socket. the voltages available are shown in the status register. bit 7 stop clock this bit is not implemented in the cl-pd6833. bits 31:8 reserved bit 6 bit 5 bit 4 voltage 000 0 v 0 0 1 reserved 0 1 0 5.0 v 0 1 1 3.3 v 100111 reserved
advance data book v0.3 june 1998 84 cardbus registers cl-pd6833 pci-to-cardbus host adapter notes
june 1998 85 advance data book v0.3 operation registers cl-pd6833 pci-to-cardbus host adapter 7. operation registers in i/o mode, the cl-pd6833 internal device control, window mapping, extension, and timing regis- ters are accessed through a pair of operation registers an index register and a data register. the index register is accessed at the address that is programmed in the i/o base address register, and the data register (see page 90 ) is accessed by adding 1 to the programmed address in the i/o base address register. figure 7-1. operation registers as pci doubleword i/o space at i/o base address register (programmed at con?guration space, offset 44h) 7.1 index bits 5:0 register index these bits determine which of the 64 possible socket-speci?c registers are accessed when the data register is next accessed by the processor. note that some values of the register index ?eld are reserved (see table 7-1 on page 86 ). bits 7:6 socket index these bits determine which set of socket-speci?c registers are selected. the index register value determines which internal register should be accessed (read or written) in response to each cpu access of the data register. each of the two possible pc card sockets is allocated 64 of the 256 locations in the internal register index space. figure 7-2. socket and register index space register name: index i/o index: n/a register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 socket index register index r/w:00 r/w:000000 index register data to/from ignored indexed register 1 + i/o base address i/o base address 3 + i/o base address 2 + i/o base address sockets 0C3 ignored socket b registers socket a registers 00h 3fh 40h 80h 7fh ffh
advance data book v0.3 june 1998 86 operation registers cl-pd6833 pci-to-cardbus host adapter when viewed as a 7-bit value, the contents of this register completely specify a single internal-register byte. for example, at reset, when the value of this register is in the range 00hC3fh, the socket a register is selected (socket index bit is 0), and when the value of this register is in the range 40hC7fh, the socket b register is selected (socket index bit is 1). the internal register that is accessed when the cpu reads or writes the data register is determined by the current value of the index register, as follows: table 7-1. index registers register name i/o index value six-bit value memory offset value chapter page chip revision 00h a 800h a chapter 8, device control registers 91 interface status 01h 801h 92 power control 02h 802h 94 interrupt and general control 03h 803h 96 card status change 04h 804h 98 management interrupt con?guration 05h 805h 99 mapping enable 06h 806h 101 i/o window control 07h 807h chapter 10, general window mapping registers 105 gen map 5 start address low 08h 808h 125 gen map 5 start address high 09h 809h 126 gen map 5 end address low 0ah 80ah 127 gen map 5 end address high 0bh 80bh 128 gen map 6 start address low 0ch 80ch 125 gen map 6 start address high 0dh 80dh 126 gen map 6 end address low 0eh 80eh 127 gen map 6 end address high 0fh 80fh 128 gen map 0 start address low 10h 810h 125 gen map 0 start address high 11h 811h 126 gen map 0 end address low 12h 812h 127 gen map 0 end address high 13h 813h 128 gen map 0 offset address low 14h 814h 123 gen map 0 offset address high 15h 815h 124 misc control 1 16h 816h chapter 11, extension registers 132 fifo control 17h 817h 134 gen map 1 start address low 18h 818h chapter 10, general window mapping registers 125 gen map 1 start address high 19h 819h 126 gen map 1 end address low 1ah 81ah 127 gen map 1 end address high 1bh 81bh 128 gen map 1 offset address low 1ch 81ch 123 gen map 1 offset address high 1dh 81dh 124 misc control 2 1eh a 81eh a chapter 11, extension registers 136 chip information 1fh a 81fh a 137
june 1998 87 advance data book v0.3 operation registers cl-pd6833 pci-to-cardbus host adapter gen map 2 start address low 20h 820h chapter 10, general window mapping registers 125 gen map 2 start address high 21h 821h 126 gen map 2 end address low 22h 822h 127 gen map 2 end address high 23h 823h 128 gen map 2 offset address low 24h 824h 123 gen map 2 offset address high 25h 825h 124 ata control 26h 826h chapter 11, extension registers 138 scratchpad 27h 827h C C gen map 3 start address low 28h 828h chapter 10, general window mapping registers 125 gen map 3 start address high 29h 829h 126 gen map 3 end address low 2ah 82ah 127 gen map 3 end address high 2bh 82bh 128 gen map 3 offset address low 2ch 82ch 123 gen map 3 offset address high 2dh 82dh 124 table 7-1. index registers (cont.) register name i/o index value six-bit value memory offset value chapter page
advance data book v0.3 june 1998 88 operation registers cl-pd6833 pci-to-cardbus host adapter extended index: 2eh C chapter 11, extension registers 140 scratchpad reserved reserved extension control 1 reserved gen map 0 upper address gen map 1 upper address gen map 2 upper address gen map 3 upper address gen map 4 upper address reserved reserved reserved pin multiplex control 0 pin multiplex control 1 gpio output control gpio input control gpio output data gpio input data prefetch window register gen map 5 upper address gen map 6 upper address pci space control pc card space control window type select misc. control 3 smb power control address gen map 0 extra control gen map 1 extra control gen map 2 extra control gen map 3 extra control gen map 4 extra control gen map 5 extra control gen map 6 extra control extension card status change misc. control 4 misc. control 5 misc. control 6 mask revision byte product id byte device capability byte a device capability byte b device implementation byte a device implementation byte b device implementation byte c device implementation byte d extended index 00h extended index 01h extended index 02h extended index 03h extended index 04h extended index 05h extended index 06h extended index 07h extended index 08h extended index 09h extended index 0ah extended index 0bh extended index 0chC17h extended index18h extended index19h extended index 1ah extended index 1bh extended index 1chC1fh extended index 20h extended index 21h extended index 22h extended index 23h extended index 24h extended index 25h extended index 26h extended index 27h extended index 28h extended index 29h extended index 2ah extended index 2bh extended index 2ch extended index 2dh extended index 2eh extended index 2fh extended index 30h extended index 31h extended index 34h extended index 35h extended index 36h extended index 37h extended index 38h extended index 39h extended index 3ah extended index 3bh 900h reserved reserved 903h reserved 840h 841h 842h 843h 844h 90ah 90bh reserved 914h 915h 918h 919h 91ah 91bh 91chC91fh 845h 846h 922h 923h 924h 925h 926h 927h 928h 929h 92ah 92bh 92ch 92dh 92eh 92fh 930h 931h 934h 935h 936h 937h 938h 939h 93ah 93bh C C C 143 C 143 143 143 143 143 C C C 144 146 147 147 148 148 149 143 143 149 150 150 151 153 154 154 154 154 154 154 154 156 157 158 158 159 160 161 162 163 164 165 166 extended data 2fh C 141 gen map 4 start address low 30h 830h chapter 10, general window mapping registers 125 gen map 4 start address high 31h 831h 126 gen map 4 end address low 32h 832h 127 gen map 4 end address high 33h 833h 128 gen map 4 offset address low 34h 834h 123 gen map 4 offset address high 35h 835h 124 table 7-1. index registers (cont.) register name i/o index value six-bit value memory offset value chapter page
june 1998 89 advance data book v0.3 operation registers cl-pd6833 pci-to-cardbus host adapter a this register affects both sockets (it is not speci?c to either socket). gen map 5 offset address low 36h 836h chapter 10, general window mapping registers 123 gen map 5 offset address high 37h 837h 124 gen map 6 offset address low 38h 838h 123 gen map 6 offset address high 39h 839h 124 setup timing 0 3ah 83ah chapter 12, timing registers 167 command timing 0 3bh 83bh 168 recovery timing 0 3ch 83ch 169 setup timing 1 3dh 83dh 167 command timing 1 3eh 83eh 168 recovery timing 1 3fh 83fh 169 reserved 905hC909h C C reserved 916hC917h C C reserved 920hC921h C C scratchpad 90chC913h C C reserved 847hC8ffh C C reserved 93chCfffh C C table 7-1. index registers (cont.) register name i/o index value six-bit value memory offset value chapter page
advance data book v0.3 june 1998 90 operation registers cl-pd6833 pci-to-cardbus host adapter 7.2 data the data register is accessed at i/o base address + 1. this register indicates the contents of the register at the socket/register index selected by the index register. register name: data i/o index: n/a register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data
june 1998 91 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter 8. device control registers 8.1 chip revision bits 3:0 revision this ?eld indicates the compatibility of the cl-pd6833 with the intel 82365sl a-step. bits 5:4 reserved these bits always read 0s. bits 7:6 interface id these bits identify the type of interface this controller supports. the cl-pd6833 supports both memory and i/o interface pc cards. a value for the current stepping only. table 8-1. device control registers quick reference register name i/o index memory offset page number chip revision 00h 800h 91 interface status 01h 801h 92 power control pme _cxt 02h 802h 94 interrupt and general control pme_cxt 03h 803h 96 card status change pme_cxt 04h 804h 98 management interrupt con?guration pme_cxt 05h 805h 99 mapping enable 06h C 101 register name: chip revision i/o index: 00h memory offset: 800h register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 interface id reserved reserved revision r:10 r:0 r:0 r:0010 a bit 7 bit 6 interface supported 0 0 i/o only 0 1 memory only 1 0 memory and i/o 1 1 reserved
advance data book v0.3 june 1998 92 device control registers cl-pd6833 pci-to-cardbus host adapter 8.2 interface status bits 1:0 battery voltage detect in memory card interface mode, these bits are used by pc card support software and ?rmware to indicate the remaining capacity of the battery in the pc cards. in i/o card interface mode, bit 0 indicates the state of the bvd1/stschg#/ri# pin (see page 20 ). bit 1 status is not valid in i/o card interface mode. bits 3:2 card detect these bits indicate the state of the cd1# and cd2# pins (see page 18 ). a bit 7 always reads 1 on the cl-pd6833. b bit 5 indicates the value of the rdy/ireq# pin (see page 18 ) in pc card 16 mode. in i/o card mode, this bit is used to identify the source of interrupt request either from socket a or b. in i/o card mode, this bit always indicates the inverted state of th e rdy/bsy intr# pin. c bit 4 indicates the value of the wp/iois16# pin (see page 18 ). d bits 3:2 indicate the inversion of the values of the cd1# and cd2# pins (see page 18 ). e bits 1:0 indicate the values of the bvd1/stschg#/ri# and bvd2/spkr#/led# pins (see page 19 ). register name: interface status i/o index: 01h memory offset: 801h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy wp cd2# cd1# bvd2 bvd1 reserved card power on ready/busy* / intr. request status write protect card detect battery voltage detect r:1 a r:0 r b r c r d r e bvd2 level bvd1 level bit 1 bit 0 pcmcia interpretation low low 0 0 card data lost low high 0 1 battery low warning high low 1 0 card data lost high high 1 1 battery/data okay cd2# level cd1# level bit 3 bit 2 card detect status high high 0 0 either no card, or card is not fully inserted high low 0 1 card is not fully inserted low high 1 0 card is not fully inserted low low 1 1 card is fully inserted
june 1998 93 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter bit 4 write protect in memory card interface mode, this bit indicates the state of the wp/iois16# pin (see page 18 ) on the card. this bit is not valid in i/o card interface mode. bit 5 ready / busy* / interrupt request status in memory card interface mode, this bit indicates the state of the rdy/ireq# pin (see page 18 ) on the card. this bit reads the state of the interrupt request in the i/o mode of operation. this bit can be used to examine the source of the interrupt if the card holds the interrupt request line ac- tive until the interrupt is serviced. this bit represents the inverted realtime value of the interrupt request pin. bit 6 card power on this status bit indicates whether power to the card is on. refer to table 8-2 for more details. bit 7 reserved this bit always reads 1. 0 card is not write-protected. 1 card is write-protected. 0 card is not ready. 1 card is ready. 0 power to the card is not on. 1 power to the card is on.
advance data book v0.3 june 1998 94 device control registers cl-pd6833 pci-to-cardbus host adapter 8.3 power control pme _cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. this register is write-protected by writes to the event force register. the register is not write protected when a cv test completes. cv test can be started by a card insertion or by a write to bit 14 of the event force register. use either the control register (see page 82 ) or this power control register to set card power. do not use both registers. a this only applies to pc card 16 (r2) cards. register name: power control pme_cxt i/o index: 02h memory offset: 802h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 card enable compatibility reserved v cc power compatibility v pp 1 power r/w:0 r/w:0 r/w:0 r/w:0 r/w:00 r/w:00 table 8-2. enabling of socket power commands rst# level both cd1# and cd2# are active (low) power control register interface status register (see page 92 ) v cc command to power device v pp command to power device v cc power (bit 4) card power on (bit 6) low x x 0 inactive (high) inactive (low) high x 0 0 inactive (high) inactive (low) high no x x inactive (high) inactive (low) high yes 1 1 activated by bit 1 of the misc control 1 register activated by bits 1 and 0 of the power control register table 8-3. enabling of pc card output signals to socket rst# level both cd1# and cd2# are active (low) power control register state of the cl-pd6833 v cc command to power device v cc power (bit 4) card enable (bit 7 a ) low x x x high-impedance high no x x high-impedance high yes 0 0 high-impedance high yes 0 1 enabled high yes 1 0 high-impedance high yes 1 1 enabled
june 1998 95 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter bits 1:0 v pp 1 power these bits control the power to the v pp 1 pin of the pc card. bits 3:2 compatibility bits bit 4 v cc power setting this bit to 1 applies power to the card. the v cc 3.3-v bit (see page 132 ) determines whether 3.3 v or 5 v power is applied. note that this bit is reset to 0 when a card is removed from the socket. this bit is locked by the v cc power lock bit (bit 0 of the extension control 1 register, memory offset 903h). bit 5 reserved bit 6 compatibility bit bit 7 card enable this bit only applies to r2 cards. when this bit is 1, the outputs to the pc card are enabled if a card is present and card power is being supplied. the pins affected include ce2#, ce1#, iord#, iowr#, oe#, reg#, reset, a[25:0], d[15:0], and we#. a this state exists under conditions where v pp 1 power is activated. see table 8-2 . bit 1 bit 0 vpp_pgm vpp_vcc pc card intended socket function 0 0 inactive (low) inactive (low) 0 v to pc card socket v pp 1 pin 0 1 inactive (low) active (high) a selected card v cc to pc card socket v pp 1 pin 1 0 active (high) a inactive (low) +12 v to pc card socket v pp 1 pin 1 1 inactive (low) inactive (low) 0 v to pc card socket v pp 1 pin 0 power is not applied to the card. 1 power is applied to the card, if cd2# and cd1# are active low, then the selected v cc voltage is applied. 0 outputs to the card socket are not enabled and are ?oating. 1 outputs to the card socket are enabled if cd1# and cd2# are active low and bit 4 is 1.
advance data book v0.3 june 1998 96 device control registers cl-pd6833 pci-to-cardbus host adapter 8.4 interrupt and general control pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 3:0 pc card irq selection note: this is for i/o card interface mode (bit 5 of this register is 1). these bits determine which irq occurs when the card causes an interrupt through the rdy/ireq# pin on the pcmcia socket when serial interrupt signalling is used. in pci interrupt signalling mode, these bits have no effect. register name: interrupt and general control pme_cxt i/o index: 03h memory offset: 803h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ring indicate enable card reset* card is i/o compatibility pc card irq selection r/w:0 r/w:0 r/w:0 r/w:0 r/w:0000 bit 3 bit 2 bit 1 bit 0 irq selection 0000irq disabled 0001irq1 for pci/way operation, reserved for other modes 0010smi for pci/way operation, reserved for other modes 0011irq3 0100irq4 0101irq5 0110irq6 for pci/way operation, reserved for other modes 0111irq7 1000irq8 for pci/way operation, reserved for other modes 1001irq9 1010irq10 1011irq11 1100irq12 1101irq13 for pci/way operation, reserved for other modes 1110irq14 1111irq15
june 1998 97 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter bit 4 compatibility bit bit 5 card is i/o this bit determines how dual-function socket interface pins are used. for more information on spe- ci?c pins, refer to table 2-2 on page 15 . bit 6 card reset* this bit determines whether the reset signal (see page 19 ) to the card is active or inactive. when the card enable bit (see page 95 ) is 0, the reset signal to the card is high-impedance. see chapter 14, ata mode operation for further description of ata mode functions. bit 7 ring indicate enable in r2 i/o card interface mode, this bit allows the bvd1/stschg#/ri# pin to be programmed as an active-low ring indicate input. when this bit is set to 1, the level on this input passes through to the pme# output. 0 sets memory card interface mode. the card socket is con?gured to support memory-only-type cards. all dual-function socket interface pins are de?ned to perform memory-only-type interface functions. 1 sets i/o card interface mode. the card socket is con?gured to support combined i/o-and-memory- type cards. all dual-function socket interface pins are de?ned to perform all i/o and basic memory type interface functions. 0 the reset signal to the card socket is set active (high for normal, low for ata mode). 1 the reset signal to the card socket is set inactive (low for normal, high for ata mode). 0 bvd1/stschg#/ri# pin is status change function. 1 bvd1/stschg#/ri# pin is ring indicate input pin from card.
advance data book v0.3 june 1998 98 device control registers cl-pd6833 pci-to-cardbus host adapter 8.5 card status change pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. this register indicates the source of a management interrupt generated by the cl-pd6833. bit 0 battery dead or status change in memory card interface mode, this bit is set to 1 when the bvd1/stschg#/ri# pin (see page 20 ) changes from high to low, indicating a battery dead condition. in i/o card interface mode, this bit is set to 1 when the bvd1/stschg#/ri# pin changes from either high to low or low to high. in i/o card interface mode, the function of this bit is not affected by bit 7 of the interrupt and general control register. this bit is reset to 0 whenever this register is read. bit 1 battery warning change in memory card interface mode, this bit is set to 1 when the bvd2/spkr#/led# pin changes from high to low, indicating a battery warning. this bit is not valid in i/o card interface mode. this bit is reset to 0 whenever this register is read. bit 2 ready change this bit is 1 when a change has occurred on the rdy/ireq# pin (see page 18 ). this bit is reset to 0 whenever this register is read. this bit is not valid in i/o card interface mode. bit 3 card detect change this bit is set to 1 when a change has occurred on the cd1# or cd2# pin (see page 18 ). this bit is reset to 0 whenever this register is read. bits 7:4 reserved these bits read 0s. register name: card status change pme_cxt i/o index: 04h memory offset: 804h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved card detect change ready change battery warning change battery dead or status change r:0 r:0 r:0 r:0 r:0 r:0 r:0 r:0 0 a transition (from high to low in memory card interface mode or either high to low or low to high in i/o card interface mode) on the bvd1/stschg#/ri# pin has not occurred since this register was last read. 1 a transition on the bvd1/stschg#/ri# pin has occurred. 0 a transition (from high to low) on the bvd2/spkr#/led# pin has not occurred since this register was last read. 1 a transition on the bvd2/spkr#/led# pin has occurred. 0 a transition on the rdy/ireq# pin has not occurred since this register was last read. 1 a transition on the rdy/ireq# pin has occurred. 0 a transition on neither the cd1# nor the cd2# pin has occurred since this register was last read. 1 a transition on either the cd1# or the cd2# pin or both has occurred.
june 1998 99 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter 8.6 management interrupt con?guration pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. this register controls which status changes cause management interrupts. they also control the pin loca- tion where the management interrupts appear. bit 0 battery dead or status change enable when this bit is 1, a management interrupt occurs when the card status change registers bat- tery dead or status change bit (see page 98 ) is 1. this allows management interrupts to be gen- erated on changes in level of the bvd1/stschg#/ri# pin. bit 1 battery warning enable when this bit is 1, a management interrupt occurs if the card status change registers battery warning change bit (see page 98 ) is 1. this allows management interrupts to be generated on changes in level of the bvd2/spkr#/led# pin. this bit is not valid in i/o card interface mode. bit 2 ready enable when this bit is 1, a management interrupt occurs when the card status change registers ready change bit (see page 98 ) is 1. this allows management interrupts to be generated on changes in level of the rdy/ireq# pin. this bit is not valid in i/o card interface mode.this bit ap- plies to memory mode only. bit 3 card detect enable when this bit is 1, a management interrupt occurs when the card status change registers card detect change bit (see page 98 ) is 1. this allows management interrupts to be generated on changes in level of the cd1# and cd2# pins. register name: management interrupt configuration pme_cxt i/o index: 05h memory offset: 805h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 management irq card detect enable ready enable battery warning enable battery dead or status change enable r/w:0000 r/w:0 r/w:0 r/w:0 r/w:0 0 battery dead or status change management interrupt is disabled. 1 if the battery dead or status change bit is 1, a management interrupt occurs. 0 battery warning change management interrupt is disabled. 1 if the battery warning change bit is 1, a management interrupt occurs. 0 ready change management interrupt is disabled. 1 if the ready change bit is 1, a management interrupt occurs. 0 card detect change management interrupt is disabled. 1 if the card detect change bit is 1, a management interrupt occurs.
advance data book v0.3 june 1998 100 device control registers cl-pd6833 pci-to-cardbus host adapter bits 7:4 management irq these bits determine which interrupt pin is used for card status change management interrupts in serial interrupt modes. in pci interrupt signalling mode, management interrupts are signalled on inta# for socket a and intb# for socket b. if the ri_out feature is enabled on intb#, all socket b card and management interrupts directed to intb# are rerouted to inta#. bit 7 bit 6 bit 5 bit 4 interrupt pin 0000irq disabled 0001irq1 for pci/way operation, reserved for others 0010smi for pci/way operation, reserved for others 0011irq3 0100irq4 0101irq5 0110irq6 for pci/way operation, reserved for others 0111irq7 1000irq8 for pci/way operation, reserved for others 1001irq9 1010irq10 1011irq11 1100irq12 1101irq13 for pci/way operation, reserved for others 1110irq14 1111irq15
june 1998 101 advance data book v0.3 device control registers cl-pd6833 pci-to-cardbus host adapter 8.7 mapping enable bit 0 memory map 0 enable when this bit is 1, the memory window mapping registers for memory window 0 are enabled and the controller responds to memory accesses in the memory space de?ned by those registers. bit 1 memory map 1 enable when this bit is 1, the memory window mapping registers for memory window 1 are enabled and the controller responds to memory accesses in the memory space de?ned by those registers. bit 2 memory map 2 enable when this bit is 1, the memory window mapping registers for memory window 2 are enabled and the controller responds to memory accesses in the memory space de?ned by those registers. bit 3 memory map 3 enable when this bit is 1, the memory window mapping registers for memory window 3 are enabled and the controller responds to memory accesses in the memory space de?ned by those registers. bit 4 memory map 4 enable when this bit is 1, the memory window mapping registers for memory window 4 are enabled and the controller responds to memory accesses in the memory space de?ned by those registers. bit 5 compatibility bit register name: mapping enable i/o index: 06h memory offset: 806h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o map 1 enable i/o map 0 enable compatibility memory map 4 enable memory map 3 enable memory map 2 enable memory map 1 enable memory map 0 enable r/w:0 r/w:0 r:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 memory window mapping registers for memory window 0 disabled. 1 memory window mapping registers for memory window 0 enabled. 0 memory window mapping registers for memory window 1 disabled. 1 memory window mapping registers for memory window 1 enabled. 0 memory window mapping registers for memory window 2 disabled. 1 memory window mapping registers for memory window 2 enabled. 0 memory window mapping registers for memory window 3 disabled. 1 memory window mapping registers for memory window 3 enabled. 0 memory window mapping registers for memory window 4 disabled. 1 memory window mapping registers for memory window 4 enabled.
advance data book v0.3 june 1998 102 device control registers cl-pd6833 pci-to-cardbus host adapter bit 6 i/o map 0 enable when this bit is 1, the i/o window mapping registers for i/o window 0 are enabled and the con- troller responds to i/o accesses in the i/o space de?ned by those registers. bit 7 i/o map 1 enable when this bit is 1, the i/o window mapping registers for i/o window 1 are enabled and the con- troller responds to i/o accesses in the i/o space de?ned by those registers. 0 i/o window mapping registers for i/o window 0 disabled. 1 i/o window mapping registers for i/o window 0 enabled. 0 i/o window mapping registers for i/o window 1 disabled. 1 i/o window mapping registers for i/o window 1 enabled.
june 1998 103 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9. window mapping registers chapter 9 and chapter 10 discuss the window mapping technique for pc card application. chapter 9 discusses the conventional or standard method for mapping windows. this method is featured in all earlier versions of cirrus logic pc card products and is also 82365slCcompatible. this method of window mapping uses seven windows to access the memory and i/o space of the pc card. the seven windows consist of two windows dedicated to the i/o space and ?ve windows dedicated to the memory space. for clarity, labels that describe the window mapping registers are consistent with those in earlier data sheets. note: as of this writing, only the standard mapping method is used by pc card software vendors. chapter 10 describes another technique for mapping the seven windows, this is called the general mapping method. the general mapping method allows for the ?exibility to map any of the seven windows as either a memory window or an i/o window. additional ?exibility allows mapping from pci memory space or pci i/o space to pc card memory space or pc card i/o space. this is shown in table 9-2 . table 9-1. window mapping registers quick reference register name i/o index memory offset page number i/o window mapping registers i/o window control 07h 807h 105 system i/o map 0C1 start address low 08h, 0ch 808h, 80ch 107 system i/o map 0C1 start address high 09h, 0dh 809h, 80dh 107 system i/o map 0C1 end address low 0ah, 0eh 80ah, 80eh 108 system i/o map 0C1 end address high 0bh, 0fh 80bh, 80fh 108 card i/o map 0C1 offset address low 36h, 38h 836h, 838h 109 card i/o map 0C1 offset address high 37h, 39h 837h, 839h 109 memory window mapping registers system memory map 0C4 start address low 10h, 18h, 20h, 28h, 30h 810h, 818h, 820h, 828h, 830h 110 system memory map 0C4 start address high 11h, 19h, 21h, 29h, 31h 811h, 819h, 821h, 829h, 831h 111 system memory map 0C4 end address low 12h, 1ah, 22h, 2ah, 32h 812h, 81ah, 822h, 82ah, 832h 112 system memory map 0C4 end address high 13h, 1bh, 23h, 2bh, 33h 813h, 81bh, 823h, 82bh, 833h 113 card memory map 0C4 offset address low 14h, 1ch, 24h, 2ch, 34h 814h, 81ch, 824h, 82ch, 834h 114 card memory map 0C4 offset address high 15h, 1dh, 25h, 2dh, 35h 815h, 81dh, 825h, 82dh, 835h 115
advance data book v0.3 june 1998 104 window mapping registers cl-pd6833 pci-to-cardbus host adapter note: the general mapping method is not currently used by pc card software vendors. table 9-2 shows the different registers that have to be programmed to use the various ?avors of the standard and general mapping methods. the general window mapping registers are ?rst presented describing the functionality of the registers when con?gured in i/o mode. thereafter, the same register functionality is described when con?gured in memory mode. this facilitates understanding since the bit assignments and de?nitions of these registers are different in the i/o mode and memory mode. note: a combination of the standard mapping method and general mapping method can be used. table 9-2. window mapping registers window type select pci space control pc card space control pci bus pc card window configuration reset to 0 dont care dont care i/o i/o standard mapping reset to 0 dont care dont care memory memory standard mapping set to 1 set to 1 set to 1 i/o i/o general mapping set to 1 set to 1 reset to 0 i/o memory general mapping set to 1 reset to 0 reset to 0 memory memory general mapping set to 1 reset to 0 set to 1 memory i/o general mapping
june 1998 105 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.1 i/o window mapping registers 9.1.1 i/o window control bit 0 i/o window 0 size when bit 1 of this register is 0, this bit determines the width of the data path for i/o window 0 accesses to the card. when bit 1 is 1, this bit is ignored. bit 1 auto-size i/o window 0 this bit determines the width of the data path for i/o window 0 accesses to the card. note that when this bit is 1, the iois16# signal determines the width of the data path to the card. bit 2 compatibility bit bit 3 timing register select 0 this bit determines the access timing speci?cation for i/o window 0. bit 4 i/o window 1 size when bit 5 of this register is 0, this bit determines the width of the data path for i/o window 1 accesses to the card. when bit 5 is 1, this bit is ignored. bit 5 auto-size i/o window 1 this bit determines the width of the data path for i/o window 1 accesses to the card. note that when this bit is 1, the iois16# signal determines the width of the data path to the card. register name: i/o window control i/o index: 07h memory offset: 807h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 timing register select 1 compatibility bit auto-size i/o window 1 i/o window 1 size timing register select 0 compatibility bit auto-size i/o window 0 i/o window 0 size r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 8-bit data path to i/o window 0. 1 16-bit data path to i/o window 0. 0 i/o window 0 size (see bit 0 of this register) determines the data path for i/o window 0 accesses. 1 the data path to i/o window 0 is determined by the iois16# signal returned by the card. 0 accesses made with timing speci?ed in timer set 0 registers. 1 accesses made with timing speci?ed in timer set 1 registers. 0 8-bit data path to i/o window 1. 1 16-bit data path to i/o window 1. 0 i/o window 1 size (see bit 4 of this register) determines the data path for i/o window 1 accesses. 1 the data path to i/o window 1 is determined based on iois16# returned by the card.
advance data book v0.3 june 1998 106 window mapping registers cl-pd6833 pci-to-cardbus host adapter bit 6 compatibility bit bit 7 timing register select 1 this bit determines the access timing speci?cation for i/o window 1. 0 accesses made with timing speci?ed in timer set 0 . 1 accesses made with timing speci?ed in timer set 1 .
june 1998 107 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.1.2 system i/o map 0C1 start address low there are two separate system i/o map start address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 08h system i/o map 0 start address low 0ch system i/o map 1 start address low bits 7:0 start address 7:0 this register contains the least-signi?cant byte of the address that speci?es where in the i/o space the corresponding i/o map begins. i/o accesses that are equal to or above this address and equal to or below the corresponding system i/o map end address are mapped into the i/o space of the corresponding pc card. the most-signi?cant byte is located in the system i/o map 0C1 start address high register. 9.1.3 system i/o map 0C1 start address high there are two separate system i/o map start address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 09h system i/o map 0 start address high 0dh system i/o map 1 start address high bits 7:0 start address 15:8 this register contains the most-signi?cant byte of the start address. see the description of the start address ?eld associated with bits 7:0 of the system i/o map 0C1 start address low register (on page 107 ). register name: system i/o map 0C1 start address low i/o index: 08h, 0ch memory offset: 808h, 80ch register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 7:0 r/w:00000000 register name: system i/o map 0C1 start address high i/o index: 09h, 0dh memory offset: 809h, 80dh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 15:8 r/w:00000000
advance data book v0.3 june 1998 108 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.1.4 system i/o map 0C1 end address low there are two separate system i/o map end address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 0ah system i/o map 0 end address low 0eh system i/o map 1 end address low bits 7:0 end address 7:0 this register contains the least-signi?cant byte of the address that speci?es where in the i/o space the corresponding i/o map ends. i/o accesses that are equal to or below this address and equal to or above the corresponding system i/o map start address are mapped into the i/o space of the corresponding pc card. the most-signi?cant byte is located in the system i/o map 0C1 end address high register. 9.1.5 system i/o map 0C1 end address high there are two separate system i/o map end address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 0bh system i/o map 0 end address high 0fh system i/o map 1 end address high bits 7:0 end address 15:8 this register contains the most-signi?cant byte of the end address. see the description of the end address ?eld associated with bits 7:0 of the system i/o map 0C1 end address low register (on page 108 ). register name: system i/o map 0C1 end address low i/o index: 0ah, 0eh memory offset: 80ah, 80eh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 7:0 r/w:00000000 register name: system i/o map 0C1 end address high i/o index: 0bh, 0fh memory offset: 80bh, 80fh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 15:8 r/w:00000000
june 1998 109 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.1.6 card i/o map 0C1 offset address low there are two separate card i/o map offset address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 36h card i/o map 0 offset address low 38h card i/o map 1 offset address low bits 7:1 offset address 7:1 this register contains the least-signi?cant byte of the quantity that is added to the system i/o address to determine where in the pc cards i/o map the i/o access occurs. the cl-pd6833 internally de?nes bit 0 of offset address as 0. the most-signi?cant byte is located in the card i/o map 0C1 offset address high register. bit 0 compatibility bit this bit must be programmed to 0. it does not affect the i/o offset address. 9.1.7 card i/o map 0C1 offset address high there are two separate card i/o map offset address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) card i/o map offset address high 37h card i/o map 0 offset address high 39h card i/o map 1 offset address high bits 7:0 offset address 15:8 this register contains the most-signi?cant byte of the offset address. see the description of the end address ?eld associated with bits 7:1 of the card i/o map 0C1 offset address low register (on page 109 ). a this bit must be programmed to 0. this compatibility bit does not affect i/o offset address. register name: card i/o map 0C1 offset address low i/o index: 36h, 38h memory offset: 836h, 838h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 7:1 compatibility bit a r/w:0000000 r/w:0 register name: card i/o map 0C1 offset address high i/o index: 37h, 39h memory offset: 837h, 839h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 15:8 r/w:00000000
advance data book v0.3 june 1998 110 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2 memory window mapping registers the following information about memory window mapping is important: l the memory window mapping registers determine where in the pci memory space and pc card memory space accesses occur. there are ?ve memory windows that can be used independently. l the memory windows are enabled and disabled using the mapping enable register. l to specify where in the pci space a memory window is mapped, start and end addresses are speci?ed. a memory window is selected whenever the appropriate memory map enable bit is set and the following con- ditions are true: the pci address is greater than or equal to the appropriate system memory map start address register (see section 9.2.1 ). the pci address is less than or equal to the appropriate system memory map end address register (see section 9.2.3 ). the system memory map upper address register is equal to the upper pci address. l start and end addresses are speci?ed with pci address bits 31:12. this sets the minimum size of a memory window to 4 kbytes. memory windows are speci?ed in the pci memory address space. l to ensure proper operation, none of the memory windows can overlap in the pci address space. 9.2.1 system memory map 0C4 start address low there are ?ve separate system memory map start address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 10h system memory map 0 start address low 18h system memory map 1 start address low 20h system memory map 2 start address low 28h system memory map 3 start address low 30h system memory map 4 start address low bits 7:0 start address 19:12 this register contains the least-signi?cant byte of the address that speci?es where in the memory space the corresponding memory map begins. memory accesses that are equal to or above this address and equal to or below the corresponding system memory map end address are mapped into the memory space of the corresponding pc card. the most-signi?cant four bits are located in the system memory map 0C4 start address high register. register name: system memory map 0C4 start address low i/o index: 10h, 18h, 20h, 28h, 30h memory offset: 810h, 818h, 820h, 828h, 830h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 19:12 r/w:00000000
june 1998 111 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2.2 system memory map 0C4 start address high there are ?ve separate system memory map start address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 11h system memory map 0 start address high 19h system memory map 1 start address high 21h system memory map 2 start address high 29h system memory map 3 start address high 31h system memory map 4 start address high bits 3:0 start address 23:20 this ?eld contains the most-signi?cant four bits of the start address. see the description of the start address ?eld associated with bits 7:0 of the system memory map 0C4 start address low register (on page 110 ). bits 5:4 scratchpad bits bit 6 compatibility bit bit 7 window data size this bit determines the data path size to the card. register name: system memory map 0C4 start address high i/o index: 11h, 19h, 21h, 29h, 31h memory offset: 811h, 819h, 821h, 829h, 831h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 window data size compatibility bit scratchpad bits start address 23:20 r/w:0 r/w:0 r/w:00 r/w:0000 0 8-bit data path to the card. 1 16-bit data path to the card.
advance data book v0.3 june 1998 112 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2.3 system memory map 0C4 end address low there are ?ve separate system memory map end address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 12h system memory map 0 end address low 1ah system memory map 1 end address low 22h system memory map 2 end address low 2ah system memory map 3 end address low 32h system memory map 4 end address low bits 7:0 end address 19:12 this register contains the least-signi?cant byte of the address that speci?es where in the memory space the corresponding memory map ends. memory accesses that are equal to or below this address and equal to or above the corresponding system memory map start address are mapped into the memory space of the corresponding pc card. the most-signi?cant four bits are located in the system memory map 0C4 end address high register. register name: system memory map 0C4 end address low i/o index: 12h, 1ah, 22h, 2ah, 32h memory offset: 812h, 81ah, 822h, 82ah, 832h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 19:12 r/w:00000000
june 1998 113 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2.4 system memory map 0C4 end address high there are ?ve separate system memory map end address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 13h system memory map 0 end address high 1bh system memory map 1 end address high 23h system memory map 2 end address high 2bh system memory map 3 end address high 33h system memory map 4 end address high bits 3:0 end address 23:20 this ?eld contains the most-signi?cant four bits of the end address. see the description of the end address ?eld associated with bits 7:0 of the system memory map 0C4 end address low register. note that the upper memory addresses are stored in the system memory map upper address register. bits 5:4 scratchpad bits bits 7:6 card timer select this ?eld selects the timer set registers to control socket timing for card accesses in this window address range. this ?eld selects the timer set. timer set 0 and 1 reset to values compatible with pc card standards. mapping of bits 7:6 to timer set 0 and 1, as shown, is done for software compatibility with other older isa-bus based pc card host adapters that use isa bus wait states instead of timer set registers. register name: system memory map 0C4 end address high i/o index: 13h, 1bh, 23h, 2bh, 33h memory offset: 813h, 81bh, 823h, 82bh, 833h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 card timer select scratchpad bits end address 23:20 r/w:00 r/w:00 r/w:0000 bit 7 bit 6 timer set select 00 selects timer set 0 01 selects timer set 1 10 selects timer set 1 11 selects timer set 1
advance data book v0.3 june 1998 114 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2.5 card memory map 0C4 offset address low there are ?ve separate card memory map offset address low registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 14h card memory map 0 offset address low 1ch card memory map 1 offset address low 24h card memory map 2 offset address low 2ch card memory map 3 offset address low 34h card memory map 4 offset address low bits 7:0 offset address 19:12 this register contains the least-signi?cant byte of the quantity that is added to the system memory address that determines where in the pc card memory map the memory access occurs. the most-signi?cant six bits are located in the card memory map 0C4 offset address high register. register name: card memory map 0C4 offset address low i/o index: 14h, 1ch, 24h, 2ch, 34h memory offset: 814h, 81ch, 824h, 82ch, 834h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 19:12 r/w:00000000
june 1998 115 advance data book v0.3 window mapping registers cl-pd6833 pci-to-cardbus host adapter 9.2.6 card memory map 0C4 offset address high there are ?ve separate card memory map offset address high registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) register 15h card memory map 0 offset address high 1dh card memory map 1 offset address high 25h card memory map 2 offset address high 2dh card memory map 3 offset address high 35h card memory map 4 offset address high bits 5:0 offset address 25:20 this ?eld contains the most-signi?cant six bits of the offset address. see the description of the offset address ?eld associated with bits 7:0 of the card memory map 0C4 offset address low register (on page 114 ). bit 6 reg setting this bit determines whether reg# is active for accesses made through this window. cis (card information structure) memory is accessed by setting this bit to 1. bit 7 write protect this bit determines whether writes to the card through this window are allowed. register name: card memory map 0C4 offset address high i/o index: 15h, 1dh, 25h, 2dh, 35h memory offset: 815h, 81dh, 825h, 82dh, 835h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write protect reg setting offset address 25:20 r/w:0 r/w:0 r/w:000000 0 reg# is not active for accesses made through this window. 1 reg# is active for accesses made through this window. 0 writes to the card through this window are allowed. 1 writes to the card through this window are not allowed.
advance data book v0.3 june 1998 116 window mapping registers cl-pd6833 pci-to-cardbus host adapter notes
june 1998 117 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10. general window mapping registers table 10-1. general window mapping registers quick reference register name i/o index memory offset page number general mapping registers for i/o mode gen map 0C6 start address low (i/o) 08h, 0ch, 10h, 18h, 20h, 28h, 30h 808h, 80ch, 810h, 818h, 820h, 828h, 830h 119 gen map 0C6 start address high (i/o) 09h, 0dh, 11h, 19h, 21h, 29h, 31h 809h, 80dh, 811h, 819h, 821h, 829h, 831h 120 gen map 0C6 end address low (i/o) 0ah, 0eh, 12h, 1ah, 22h, 2ah, 32h 80ah, 80eh, 812h, 81ah, 822h, 82ah, 832h 121 gen map 0C6 end address high (i/o) 0bh, 0fh, 13h, 1bh, 23h, 2bh, 33h 80bh, 80fh, 813h, 81bh, 823h, 82bh, 833h 122 gen map 0C6 offset address low (i/o) 14h, 1ch, 24h, 2ch, 34h, 36h, 38h 814h, 81ch, 824h, 82ch, 834h, 836h, 838h 123 gen map 0C6 offset address high (i/o) 15h, 1dh, 25h, 2dh, 35h, 37h, 39h 815h, 81dh, 825h, 82dh, 835h, 837h, 839h 124 general mapping register for memory mode gen map 0C6 start address low (memory) 08h, 0ch, 10h, 18h, 20h, 28h, 30h 808h, 80ch, 810h, 818h, 820h, 828h, 830h 125 gen map 0C6 start address high (memory) 09h, 0dh, 11h, 19h, 21h, 29h, 31h 809h, 80dh, 811h, 819h, 821h, 829h, 831h 126 gen map 0C6 end address low (memory) 0ah, 0eh, 12h, 1ah, 22h, 2ah, 32h 80ah, 80eh, 812h, 81ah, 822h, 82ah, 832h 127 gen map 0C6 end address high (memory) 0bh, 0fh, 13h, 1bh, 23h, 2bh, 33h 80bh, 80fh, 813h, 81bh, 823h, 82bh, 833h 128 gen map 0C6 offset address low (memory) 14h, 1ch, 24h, 2ch, 34h, 36h, 38h 814h, 81ch, 824h, 82ch, 834h, 836h, 838h 129 gen map 0C6 offset address high (memory) 15h, 1dh, 25h, 2dh, 35h, 37h, 39h 815h, 81dh, 825h, 82dh, 835h, 837h, 839h 130
advance data book v0.3 june 1998 118 general window mapping registers cl-pd6833 pci-to-cardbus host adapter the following information about i/o window mapping is important: l the i/o window mapping registers determine where in the pci i/o space and pc card i/o space accesses occur. on reset, there are two i/o windows that can be used independently. l in addition, depending on the pc card space control, pci space control, and window type select registers, all mapping registers can be de?ned as i/o window mapping registers. this provides ?ve additional i/o windows that can be used independently. a total of seven i/o windows can be realized. l all the i/o window mapping registers have dual functionality. the functions are determined by the pc card space control, pci space control, and window type select registers . at reset the window type select register is set to 00h. this con?gures the i/o and memory windows to be compatible with the cl-pd672x products. when a bit in the window type select register is set, the corresponding window can be programmed using the pc card space control and pci space control registers to respond to i/o or memory commands on the pci bus and to present these cycles to the pc card 16 socket as either memory or i/o cycles. to facilitate this operation anytime, a bit is set in the window type select register. the attributes for timer selection and the size of the data for a window are programmed in the gen map extra control registers. l the i/o windows are enabled and disabled using the mapping enable register (see page 101 ). l to specify where in the pci space an i/o window is mapped, start and end addresses are speci?ed. an i/o window is selected whenever the appropriate gen map enable bit is set and the following conditions are true: the pci address is greater than or equal to the appropriate gen map start address register. the pci address is less than or equal to the appropriate gen map end address register. the upper 16 bits of the pci address are all 0s. l to specify where in the pci space a memory window is mapped, start and end addresses are speci?ed. a memory window is selected whenever the appropriate memory map enable bit is set and the following conditions are true: the pci address is greater than or equal to the appropriate system memory map start address register (see page 110 ). the pci address is less than or equal to the appropriate system memory map end address register (see page 112 ). the system memory map upper address register is equal to the upper pci address. start and end addresses are speci?ed with pci address bits 31:12. this sets the minimum size of a memory window to 4 kbytes. memory windows are speci?ed in the pci memory address space. l to ensure proper operation, none of the i/o windows can overlap in the pci address space. l in this speci?cation, references to i/o window 0 pertain to gen map 5 and i/o window 1 corresponds to gen map 6. memory windows 0C4 correspond to gen map 0C4. caution: be sure that the i/o windows do not map to the i/o base address register programmed at offset 44h in the con?guration space.
june 1998 119 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1 general mapping registers for i/o mode 10.1.1 gen map 0C6 start address low (i/o) there are seven separate gen map start address low registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 start address 7:0 (i/o) this register contains the least-signi?cant byte of the address that speci?es where the i/o space corresponding to the i/o map begins. i/o accesses that are equal or above this address and equal or below the corresponding gen map end address are mapped into the i/o or memory space of the corresponding pc card depending on the appropriate bit of the pc card space control register. register name: gen map 0C6 start address low (i/o) i/o index: 08h, 0ch, 10h, 18h, 20h, 28h, 30h memory offset: 808h, 80ch, 810h, 818h, 820h, 828h, 830h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 7:0 (i/o) r/w:00000000 index memory offset gen map start address low default operation 08h 808h gen map 5 start address low i/o window 0 0ch 80ch gen map 6 start address low i/o window 1 10h 810h gen map 0 start address low memory window 0 18h 818h gen map 1 start address low memory window 1 20h 820h gen map 2 start address low memory window 2 28h 828h gen map 3 start address low memory window 3 30h 830h gen map 4 start address low memory window 4
advance data book v0.3 june 1998 120 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1.2 gen map 0C6 start address high (i/o) there are seven separate gen map start address high registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 start address 15:8 (i/o) this register contains the most-signi?cant byte of the address of the i/o space start address. register name: gen map 0C6 start address high (i/o) i/o index: 09h, 0dh, 11h, 19h, 21h, 29h, 31h memory offset: 809h, 80dh, 811h, 819h, 821h, 829h, 831h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 15:8 (i/o) r/w:00000000 index memory offset gen map start address high default operation 09h 809h gen map 5 start address high i/o window 0 0dh 80dh gen map 6 start address high i/o window 1 11h 811h gen map 0 start address high memory window 0 19h 819h gen map 1 start address high memory window 1 21h 821h gen map 2 start address high memory window 2 29h 829h gen map 3 start address high memory window 3 31h 831h gen map 4 start address high memory window 4
june 1998 121 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1.3 gen map 0C6 end address low (i/o) there are seven separate gen map end address low registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 end address 7:0 (i/o) this register contains the least-signi?cant byte of the address that speci?es where the i/o space corresponding to the i/o map ends. i/o accesses that are equal or below this address and equal or above the corresponding gen map start address are mapped into the i/o or memory space of the corresponding pc card. register name: gen map 0C6 end address low (i/o) i/o index: 0ah, 0eh, 12h, 1ah, 22h, 2ah, 32h memory offset: 80ah, 80eh, 812h, 81ah, 822h, 82ah, 832h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 7:0 (i/o) r/w:00000000 index memory offset gen map end address low default operation 0ah 80ah gen map 5 end address low i/o window 0 0eh 80eh gen map 6 end address low i/o window 1 12h 812h gen map 0 end address low memory window 0 1ah 81ah gen map 1 end address low memory window 1 22h 822h gen map 2 end address low memory window 2 2ah 82ah gen map 3 end address low memory window 3 32h 832h gen map 4 end address low memory window 4
advance data book v0.3 june 1998 122 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1.4 gen map 0C6 end address high (i/o) there are seven separate gen map end address high registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 end address 15:8 (i/o) this register contains the most-signi?cant byte of the address of the i/o space end address. register name: gen map 0C6 end address high (i/o) i/o index: 0bh, 0fh, 13h, 1bh, 23h, 2bh, 33h memory offset: 80bh, 80fh, 813h, 81bh, 823h, 82bh, 833h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 15:8 (i/o) r/w:00000000 index memory offset gen map end address high default operation 0bh 80bh gen map 5 end address high i/o window 0 0fh 80fh gen map 6 end address high i/o window 1 13h 813h gen map 0 end address high memory window 0 1bh 81bh gen map 1 end address high memory window 1 23h 823h gen map 2 end address high memory window 2 2bh 82bh gen map 3 end address high memory window 3 33h 833h gen map 4 end address high memory window 4
june 1998 123 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1.5 gen map 0C6 offset address low (i/o) there are seven separate gen map offset address low registers, each with identical ?elds. these registers are located at the following indexes: bit 0 reserved this bit must be programmed to 0 for i/o offset. bits 7:1 offset address 7:1(i/o) this register contains the least-signi?cant byte of the quantity that is added to the system address to determine where in the pc cards i/o map the i/o access occurs. a this bit must be programmed to 0 for i/o offset. register name: gen map 0C6 offset address low (i/o) i/o index: 14h, 1ch, 24h, 2ch, 34h, 36h, 38h memory offset: 814h, 81ch, 824h, 82ch, 834h, 836h, 838h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 7:1 (i/o) 0 a r/w:0000000 r/w:0 i/o index memory offset gen map offset address low default operation 14h 814h gen map 0 offset address low memory window 0 1ch 81ch gen map 1 offset address low memory window 1 24h 824h gen map 2 offset address low memory window 2 2ch 82ch gen map 3 offset address low memory window 3 34h 834h gen map 4 offset address low memory window 4 36h 836h gen map 5 offset address low i/o window 0 38h 838h gen map 6 offset address low i/o window 1
advance data book v0.3 june 1998 124 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.1.6 gen map 0C6 offset address high (i/o) there are seven separate gen map offset address high registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 offset address 15:8 (i/o) this register contains the most-signi?cant byte of the quantity that is added to the system address to determine where in the pc cards i/o map the i/o access occurs. register name: gen map 0C6 offset address high (i/o) i/o index: 15h, 1dh, 25h, 2dh, 35h, 37h, 39h memory offset: 815h, 81dh, 825h, 82dh, 835h, 837h, 839h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 15:8 (i/o) r/w:00000000 i/o index memory offset gen map offset address high default operation 15h 815h gen map 0 offset address high memory window 0 1dh 81dh gen map 1 offset address high memory window 1 25h 825h gen map 2 offset address high memory window 2 2dh 82dh gen map 3 offset address high memory window 3 35h 835h gen map 4 offset address high memory window 4 37h 837h gen map 5 offset address high i/o window 0 39h 839h gen map 6 offset address high i/o window 1
june 1998 125 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2 general mapping register for memory mode 10.2.1 gen map 0C6 start address low (memory) there are seven separate gen map start address low registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 start address 19:12 (memory) this register contains the least-signi?cant byte of the address that speci?es where the memory space of the corresponding memory map begins. memory accesses that are equal or above this address and equal or below the corresponding gen map end address are mapped into the i/o or memory space of the corresponding pc card depending on the appropriate bits of the pc card space control and window type select registers . the most-signi?cant byte is located in the gen map 0C6 start address high register. register name: gen map 0C6 start address low (memory) i/o index: 08h, 0ch, 10h, 18h, 20h, 28h, 30h memory offset: 808h, 80ch, 810h, 818h, 820h, 828h, 830h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 19:12 (memory) r/w:00000000 index memory offset gen map start address low default operation 08h 808h gen map 5 start address low i/o window 0 0ch 80ch gen map 6 start address low i/o window 1 10h 810h gen map 0 start address low memory window 0 18h 818h gen map 1 start address low memory window 1 20h 820h gen map 2 start address low memory window 2 28h 828h gen map 3 start address low memory window 3 30h 830h gen map 4 start address low memory window 4
advance data book v0.3 june 1998 126 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2.2 gen map 0C6 start address high (memory) there are seven separate gen map start address high registers, each with identical ?elds. these registers are located at the following indexes: bits 3:0 start address 23:20 this ?eld contains the most-signi?cant four bits of the memory start address. bits 5:4 scratchpad bits bit 6 compatibility bit bit 7 reserved register name: gen map 0C6 start address high (memory) i/o index: 09h, 0dh, 11h, 19h, 21h, 29h, 31h memory offset: 809h, 80dh, 811h, 819h, 821h, 829h, 831h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved compatibility bit scratchpad bits start address 23:20 r/w:0 r/w:0 r/w:00 r/w:0000 index memory offset gen map start address high default operation 09h 809h gen map 5 start address high i/o window 0 0dh 80dh gen map 6 start address high i/o window 1 11h 811h gen map 0 start address high memory window 0 19h 819h gen map 1 start address high memory window 1 21h 821h gen map 2 start address high memory window 2 29h 829h gen map 3 start address high memory window 3 31h 831h gen map 4 start address high memory window 4
june 1998 127 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2.3 gen map 0C6 end address low (memory) there are seven separate gen map end address low registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 end address 19:12 (memory) this register contains the least-signi?cant byte of the address that speci?es where in the memory space corresponding to the memory map ends. memory accesses that are equal or below this address and equal or above the corresponding gen map start address are mapped into the i/o or memory space of the corresponding pc card. the most-signi?cant bits are located in the gen map 0C6 end address high register. register name: gen map 0C6 end address low (memory) i/o index: 0ah, 0eh, 12h, 1ah, 22h, 2ah, 32h memory offset: 80ah, 80eh, 812h, 81ah, 822h, 82ah, 832h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 19:12 (memory) r/w:00000000 index memory offset gen map end address low default operation 0ah 80ah gen map 5 end address low i/o window 0 0eh 80eh gen map 6 end address low i/o window 1 12h 812h gen map 0 end address low memory window 0 1ah 81ah gen map 1 end address low memory window 1 22h 822h gen map 2 end address low memory window 2 2ah 82ah gen map 3 end address low memory window 3 32h 832h gen map 4 end address low memory window 4
advance data book v0.3 june 1998 128 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2.4 gen map 0C6 end address high (memory) there are seven separate gen map end address high registers, each with identical ?elds. these registers are located at the following indexes: bits 3:0 end address 23:20 (memory) this ?eld contains the most-signi?cant four bits of the memory end address for registers that default to memory operation. bits 5:4 scratchpad bits bits 7:6 reserved register name: gen map 0C6 end address high (memory) i/o index: 0bh, 0fh, 13h, 1bh, 23h, 2bh, 33h memory offset: 80bh, 80fh, 813h, 81bh, 823h, 82bh, 833h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scratchpad bits end address 23:20 (memory) r/w:00 r/w:00 r/w:0000 index memory offset gen map end address high default operation 0bh 80bh gen map 5 end address high i/o window 0 0fh 80fh gen map 6 end address high i/o window 1 13h 813h gen map 0 end address high memory window 0 1bh 81bh gen map 1 end address high memory window 1 23h 823h gen map 2 end address high memory window 2 2bh 82bh gen map 3 end address high memory window 3 33h 833h gen map 4 end address high memory window 4
june 1998 129 advance data book v0.3 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2.5 gen map 0C6 offset address low (memory) there are seven separate gen map offset address low registers, each with identical ?elds. these registers are located at the following indexes: bits 7:0 offset address 19:12 (memory) this register contains the least-signi?cant byte of the quantity that is added to the system address that determines where in the pcmcia cards memory map the memory access occurs. the most-signi?cant bits are located in the gen map 0C6 offset address high register. register name: gen map 0C6 offset address low (memory) i/o index: 14h, 1ch, 24h, 2ch, 34h, 36h, 38h memory offset: 814h, 81ch, 824h, 82ch, 834h, 836h, 838h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 19:12 (memory) r/w:0000000 i/o index memory offset gen map offset address low default operation 14h 814h gen map 0 offset address low memory window 0 1ch 81ch gen map 1 offset address low memory window 1 24h 824h gen map 2 offset address low memory window 2 2ch 82ch gen map 3 offset address low memory window 3 34h 834h gen map 4 offset address low memory window 4 36h 836h gen map 5 offset address low i/o window 0 38h 838h gen map 6 offset address low i/o window 1
advance data book v0.3 june 1998 130 general window mapping registers cl-pd6833 pci-to-cardbus host adapter 10.2.6 gen map 0C6 offset address high (memory) there are seven separate gen map offset address high registers, each with identical ?elds. these registers are located at the following indexes: bits 5:0 offset address 25:20 (memory) this ?eld contains the most-signi?cant six bits of the memory offset address. bit 6 reg setting this bit determines whether reg# (see page 15 ) is active for accesses made through this window. cis (card information structure) memory is accessed by setting this bit to 1. bit 7 write protect this bit determines whether writes to the card through this window are allowed. see the description of the offset address ?eld associated with bits 7:0 of the gen map 5C6 offset address low register (on page 123 ). register name: gen map 0C6 offset address high (memory) i/o index: 15h, 1dh, 25h, 2dh, 35h, 37h, 39h memory offset: 815h, 81dh, 825h, 82dh, 835h, 837h, 839h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write protect reg setting offset address 25:20 (memory) r/w:0 r/w:0 r/w:000000 i/o index memory offset gen map offset address high default operation 15h 815h gen map 0 offset address high memory window 0 1dh 81dh gen map 1 offset address high memory window 1 25h 825h gen map 2 offset address high memory window 2 2dh 82dh gen map 3 offset address high memory window 3 35h 835h gen map 4 offset address high memory window 4 37h 837h gen map 5 offset address high i/o window 0 39h 839h gen map 6 offset address high i/o window 1 0 reg# (see page 15 ) is not active for accesses made through this window. 1 reg# is active for accesses made through this window. 0 writes to the card through this window are allowed. 1 writes to the card through this window are not allowed.
june 1998 131 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11. extension registers table 11-1. extension registers quick reference register name i/o index memory offset extended index page number misc control 1 16h 816h C 132 fifo control 17h 817h C 134 misc control 2 1eh 81eh C 136 chip information 1fh 81fh C 137 ata control 26h 826h C 138 extended index 2eh, 6eh C C 140 extended data 2fh, 6fh C C 141 extension control 1 2fh 903h 03h 142 gen map 0C6 upper address (memory) 2fh 840h, 841h, 842h, 843h, 844h, 845h, 846h 05hC09h, 20h, 21h 143 pin multiplex control 0 register pme_cxt 2fh 914h C 144 pin multiplex control 1 register pme_cxt 2fh 915h C 146 gpio output control 2fh 918h 18h 147 gpio input control 2fh 919h 19h 147 gpio output data 2fh 91ah 1ah 148 gpio input data 2fh 91bh 1bh 148 prefetch window register 2fh 91ch 1ch 149 pci space control 2fh 922h 22h 149 pc card space control 2fh 923h 23h 150 window type select 2fh 924h 24h 150 misc control 3 2fh 925h 25h 151 smbus socket power control address pme_cxt 2fh 926h 26h 153 gen map 0C6 extra control (i/o) 2fh 927hC92dh 27hC2dh 154 gen map 0C6 extra control (memory) 2fh 927hC92dh 27hC2dh 155 extension card status change 2fh 92eh 2eh 156 misc control 4 2fh 92fh 2fh 157 misc control 5 2fh 930h 30h 158 misc control 6 2fh 931h 31h 158
advance data book v0.3 june 1998 132 extension registers cl-pd6833 pci-to-cardbus host adapter 11.1 misc control 1 bit 0 multimedia enable when this bit is set to 1, the host tristates address lines a[25:4]. this bit has no effect unless the multimedia arm bit is set to 1 in misc control 3 (see section 11.8.4 on page 151 ). bit 1 v cc 3.3 v pme_cxt this bit determines whether 3 v or 5 v is applied to the socket when card power is applied; this bit is used in conjunction with bit 4 of the power control register. this bit is part of the pme_cxt (pme context), a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. a bits 3:2 are valid only in external hardware interrupt signalling mode. device identi?cation and implementation scheme 159 mask revision byte 34h 934h C 159 product id byte 35h 935h C 160 device capability byte a 36h 936h C 161 device capability byte b 37h 937h C 162 device implementation byte a 38h 938h C 163 device implementation byte b 39h 939h C 164 device implementation byte c 3ah 93ah C 165 device implementation byte d 3bh 93bh C 166 register name: misc control 1 i/o index: 16h memory offset: 816h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 compatibility bit scratchpad bits speaker enable pulse system irq interrupt a pulse management interrupt a v cc 3.3 v pme_cxt multimedia enable r/w:0 r/w:00 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 socket address lines are normal. 1 socket address lines a[25:4] are high-impedance. 0 5 v activated when card power is to be applied. 1 3 v activated when card power is to be applied. table 11-1. extension registers quick reference (cont.) register name i/o index memory offset extended index page number
june 1998 133 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter bit 2 pulse management interrupt this bit is valid only in external hardware interrupt signalling mode. this bit selects level or pulse mode operation of the irq[xx] pin. note that a clock must be present on pci_clk for pulsed interrupts to work. refer to section 15.3.2 for more information on interrupt timing. figure 11-1. pulse mode interrupts bit 3 pulse system irq interrupt this bit is valid only in external hardware interrupt signalling mode. this bit selects level or pulse mode operation of the irq[xx] pins. bit 4 speaker enable this bit determines whether the card spkr# pin drives spkr_out* (see page 21 ). bits 6:5 scratchpad bits bit 7 compatibility bit 0 interrupts are passed to the irq[xx] pin as level-sensitive. 1 when an interrupt occurs, the irq[xx] pin is driven with the pulse train shown in figure 11-1 and allows for interrupt sharing. 0 interrupts are passed to the irq[xx] pin as level-sensitive. 1 when an interrupt occurs, the irq[xx] pin is driven with the pulse train shown in figure 11-1 and allows for interrupt sharing. 0 spkr_out* is high-impedance. 1 spkr_out* is driven from the xnor of spkr# from each enabled socket. irq[xx] high-z high-z high-z = high-impedance driven low driven high
advance data book v0.3 june 1998 134 extension registers cl-pd6833 pci-to-cardbus host adapter 11.2 fifo control bits 1:0 memory prefetch disable this bit disables memory prefetch when the cardbus card is bus master and is performing memory reads from host system memory. note: bits 1:0 must be set to 00 or to 11; no other combinations are allowed. bit 2 enable cardbus-to-cardbus posting this bit controls cardbus-to-cardbus memory writes. it enables the posting of memory writes when the cardbus card is bus master and is performing memory writes to the other cardbus card in the cardbus controller. a safe policy is to set this bit only when there are cards operating in 32-bit cardbus mode in both sockets. bit 3 cardbus-to-pci fifo disable this bit disables the posting of memory writes to the pci bus when the cardbus is bus master and is performing memory writes to pci host memory. bit 4 reserved this bit must be written to 0. register name: fifo control i/o index: 17h memory offset: 817h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo status / flush fifo disable memory posting disable i/o posting reserved cardbus-to- pci fifo disable enable cardbus-to- cardbus posting memory prefetch disable r/w:1 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:00 bit 1 bit 0 memory prefetch 0 0 prefetching is enabled. 1 1 prefetching by cardbus master of pci memory addresses is disabled. 0 cardbus-to-cardbus posting is disabled. this bit must be disabled (cleared to 0) if there is an r2 card in the socket being written. 1 cardbus-to-cardbus posting is enabled. this bit should be enabled only if there are cardbus cards in both sockets. 0 cardbus-to-pci posting is enabled. 1 cardbus-to-pci posting is disabled.
june 1998 135 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter bit 5 disable i/o posting this bit disables posting of i/o writes when host pci is bus master and is performing i/o writes to cardbus or r2 cards. when this bit is set, i/o writes from the pci bus to a pc card do not post to the fifo, but are issued directly to the pc card. bit 6 disable memory posting this bit disables posting of memory writes when host pci is bus master and is performing memory writes to cardbus or r2 cards. when this bit is set, memory writes from the pci bus to a pc card do not post to the fifo, but are issued directly to the pc card. bit 7 fifo status / flush fifo this bit controls fifo operation and reports fifo status. when this bit is set to 1 during write operations, all data in the fifo is lost. during read operations, when this bit is 1, the fifo is empty. during read operations when this bit is 0, the fifo has valid data. this bit is used to ensure that the fifo is empty before changing any registers; register writes are retried if the fifo is not empty. fifo contents are lost whenever any of the following occur: l rst# pin (see page 19 ) is active. l the card is removed. l v cc power bit (see page 95 ) is programmed to 0. l the flush fifo bit is set to 1. 0 posting of i/o writes is enabled. 1 posting of i/o writes is disabled. 0 posting of memory writes is enabled. 1 posting of memory writes is disabled. value i/o read i/o write 0 fifo not empty no operation occurs (default at reset) 1 fifo empty flush the fifo
advance data book v0.3 june 1998 136 extension registers cl-pd6833 pci-to-cardbus host adapter 11.3 misc control 2 bits 6:0 reserved bit 7 ri_out/intb is ri_out this bit determines the function of the ri_out/intb# pin. when this bit is set to 1, ri_out/intb# can be used to trigger restoration of system activity when a high-to-low change is detected on the bvd1/stschg#/ri# pin. bit 5 of index 03h must be set to 1 for ri to work. register name: misc control 2 i/o index: 1eh memory offset: 81eh register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ri_out/intb is ri_out reserved r/w:0 r/w:0000000 0 normal interrupt operation on the ri_out/intb# pin. 1 the ri_out/intb# pin is connected to the ring indicate pin on the system logic.
june 1998 137 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.4 chip information bit 0 dma capable a 1 in this bit indicates that the cl-pd6833 is capable of dma. bits 4:1 cl-pd6833 revision level this ?eld is 1111, indicating to software that device identi?cation registers described in section 11.9 on page 159 are to be accessed to determine the revision id. in cirrus logic pc card controllers, if bits 4:1 of the register at memory offset 81fh read back 0h, the chip information is contained in bits 3:0 of the register at memory offset 934h. bit 5 dual/single socket this bit speci?es that the cl-pd6833 supports two sockets. bits 7:6 cirrus logic host-adapter identification this ?eld identi?es a cirrus logic host-adapter device. after chip reset or when doing an i/o write to this register, the ?rst read of this register returns a 11. on the next read, this ?eld is 00. this pattern of toggling data on subsequent reads can be used by software to determine presence of a cirrus logic host adapter in a system or to determine the occurrence of a device reset. register name: chip information i/o index: 1fh memory offset: 81fh register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cirrus logic host-adapter identification dual/single socket cl-pd6833 revision level dma capable r:11 r:1 r:1111 r:1 0 chip identi?ed as a single-socket controller. 1 chip identi?ed as a dual-socket controller. 00 second read after i/o write to this register. 11 first read after i/o write to this register.
advance data book v0.3 june 1998 138 extension registers cl-pd6833 pci-to-cardbus host adapter 11.5 ata control bit 0 ata mode pme_cxt this bit recon?gures the particular socket as an ata drive interface. refer to table 14-1 on page 179 for pc card socket pin de?nitions in ata mode. this bit is part of the pme_cxt (pme context), a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bit 1 speaker is led input this bit changes the function of the bvd2/spkr#/led# pin (see page 19 ) from digital speaker input to disk status led input. when in i/o card interface mode or ata mode, setting this bit to 1 recon?gures the bvd2/spkr#/led# input pin to serve as a led# input from the socket. the level of the input then appears as an open-drain output on the led1* or led2* pin corresponding to the socket. bit 2 scratchpad bit bit 3 a21 in ata mode, the value in this bit is applied to the ata a21 pin and is vendor-speci?c. certain ata drive vendor-speci?c performance enhancements beyond the pcmcia 2.1 standard can be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 4 a22 in ata mode, the value in this bit is applied to the ata a22 pin and is vendor-speci?c. certain ata drive vendor-speci?c performance enhancements beyond the pcmcia 2.1 standard can be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 5 a23/vu in ata mode, the value in this bit is applied to the ata a23 pin and is vendor-speci?c. certain ata drive vendor-speci?c performance enhancements beyond the pcmcia 2.1 standard can be controlled through use of this bit. this bit has no hardware control function when not in ata mode. register name: ata control i/o index: 26h memory offset: 826h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a25/csel a24/m/s* a23/vu a22 a21 scratchpad bit speaker is led input ata mode pme_cxt r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 normal operation. 1 con?gures the socket interface to handle ata-type disk drives. 0 normal operation. 1 the pc card spkr# pin is used to drive the led-out* pin.
june 1998 139 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter bit 6 a24/m/s* in ata mode, the value in this bit is applied to the ata a24 pin and is vendor-speci?c. certain ata drive vendor-speci?c performance enhancements beyond the pcmcia 2.1 standard can be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 7 a25/csel in ata mode, the value in this bit is applied to the ata a25 pin and is vendor-speci?c. certain ata drive vendor-speci?c performance enhancements beyond the pcmcia 2.1 standard can be controlled through use of this bit. this bit has no hardware control function when not in ata mode.
advance data book v0.3 june 1998 140 extension registers cl-pd6833 pci-to-cardbus host adapter 11.6 extended index this register controls which of the following registers at index 2fh can be accessed: register name: extended index i/o index: 2eh, 6eh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extended index r/w:00000000 table 11-2. extended index registers register name at index 2fh extended index memory offset scratchpad 00h C reserved 01h C reserved 02h C extension control 1 03h 903h reserved 04h C gen map 0 upper address 05h 840h gen map 1 upper address 06h 841h gen map 2 upper address 07h 842h gen map 3 upper address 08h 843h gen map 4 upper address 09h 844h reserved 0ahC17h C pin multiplex control 0 C 914h pin multiplex control 1 C 915h gpio output control 18h 918h gpio input control 19h 919h gpio output data 1ah 91ah gpio input data 1bh 91bh prefetch window register 1ch 91ch gen map 5 upper address 20h 845h gen map 6 upper address 21h 846h pci space control 22h 922h pc card space control 23h 923h window type select 24h 924h
june 1998 141 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter for information on how to access these registers, see section 3.3 on page 42 . 11.7 extended data the data in this register allows the registers indicated by the extended index register to be read and written. the value of this register is the value of the register selected by the extended index register. misc control 3 25h 925h smb power control address 26h 926h gen map 0 extra control 27h 927h gen map 1 extra control 28h 928h gen map 2 extra control 29h 929h gen map 3 extra control 2ah 92ah gen map 4 extra control 2bh 92bh gen map 5 extra control 2ch 92ch gen map 6 extra control 2dh 92dh extension card status change 2eh 92eh misc control 4 2fh 92fh misc control 5 30h 930h misc control 6 31h 931h register name: extended data i/o index: 2fh, 6fh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extended data table 11-2. extended index registers (cont.) register name at index 2fh extended index memory offset
advance data book v0.3 june 1998 142 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.1 extension control 1 bit 0 v cc power lock this bit can be used to prevent card drivers from overriding the socket services task of controlling power to the card, thus preventing situations where cards are powered incorrectly. bit 1 reserved bit 2 led activity enable this bit allows the led_out* and led1* or led2* pin corresponding to the socket to re?ect any activity in the card. whenever pc card cycles are in process to or from a card in the respective sockets, led1* or led2* pin is active low. bits 4:3 reserved bit 5 pull-up control this bit turns off the pull-ups on vs2, vs1, cd2, and cd1. turning off these pull-ups can be used in addition to suspend mode to even further reduce power when cards are inserted, but no card accessibility is required. even though power may or may not still be applied, all pull-ups and their associated inputs are disabled. note that insertion or removal of a card cannot be determined when this bit is set to 1. also, when a card is already in the socket, a card detect interrupt is generated when this bit is changed from 0 to 1. bits 7:6 dreq enable these bits are used to identify which pc card 16 pin is used for dreq, and enable the dma operation of the socket. at reset these bits are reset and this disables the dreq line. when either or both of these bits are set, the dreq pin is selected by the following table. register name: extension control 1 i/o index: 2fh extended index: 03h memory offset: 903h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dreq enable pull-up control reserved led activity enable reserved v cc power lock r/w:00 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 the v cc power bit (bit 4 of power control register) is not locked. 1 the v cc power bit (bit 4 of power control register) cannot be changed by software. 0 led activity disabled. 1 led activity enabled. 0 pull-ups on vs2, vs1, cd2, and cd1 are in use. 1 pull-ups on vs2, vs1, cd2, and cd1 are turned off. bit 7 bit 6 pin used 0 0 dreq disabled 0 1 inpack# 1 0 wp/iois16 1 1 bvd2/spkr#
june 1998 143 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.2 gen map 0C6 upper address (memory) these bits are used in comparing pci address bits 31:24 for each memory window (0C6). these bits are used in conjunction with the window type select, gen map 0C6 start address, and gen 0C6 end address registers. if the window type select bit corresponding to windows 0C4 is reset, that window is a memory window and this register speci?es that windows upper address. if the window type select bit for a window is set and the corresponding bit in the pci space control register is reset, then that window is a memory window on the pci side. this register sets the upper address for that memory window. if none of the above conditions is true, then this register is ignored. register name: gen map 0C6 upper address (memory) i/o index: 2fh extended index : 05hC09h, 20h, 21h memory offset: 840h, 841h, 842h, 843h, 844h, 845h, 846h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 upper address r/w:00000000
advance data book v0.3 june 1998 144 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.3 pin multiplex control 0 register pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 1:0 inta#/led1*/gpio1 select 1:0 these bits select the function of pin 203. bits 3:2 sin#/isdat/led2*/gpio2 select 1:0 these bits select the function of pin 206. led1* and led2* features are only available in pci/way interrupt signalling mode. a the socket a led indicator, active-low od, or led_out* if con?gured for one led. a the socket b led indicator, active-low od, or led_out* if con?gured for one led (dual socket is 0). register name: pin multiplex control 0 register pme_cxt i/o index: 2fh extended index: 14h memory offset: 914h (for function 0 only) register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 led_out*/hw_susp*/ pme#/gpio4 spkr_out*/gpio3 sin#/isdat/ led2*/gpio2 inta#/led1*/gpio1 select 1 select 0 select 1 select 0 select 1 select 0 select 1 select 0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 bit 1 bit 0 pin function 0 0 inta# or led1* a 0 1 gpio1 1 0 do not program this value. 1 1 do not program this value. bit 3 bit 2 pin function 00 sin#, isdat, or led2* with control of pin characteristics per the cl-pd6833 bits a 0 1 gpio2 1 0 do not program this value. 1 1 do not program this value.
june 1998 145 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter bits 5:4 spkr_out*/gpio3 select 1:0 these bits select the function of pin 128. bits 7:6 led_out*/hw_susp*/pme#/gpio4 select 1:0 these bits select the function of pin 133. bit 5 bit 4 pin function 0 0 spkr_out* with control of pin characteristics per the cl-pd6833. 0 1 gpio3 1 0 do not program this value. 1 1 do not program this value. bit 7 bit 6 pin function 00 led_out* or hw_susp* with control of pin characteristics per the cl-pd6833 0 1 gpio4 10 pme# as de?ned by the pci speci?cation (pci power management add-on speci?cation) 1 1 do not program this value.
advance data book v0.3 june 1998 146 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.4 pin multiplex control 1 register pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 1:0 intb#/ri_out*/ pme# select 1:0 these bits select the function of pin 204. bits 7:2 reserved register name: pin multiplex control 1 register pme_cxt i/o index: 2fh extended index: 15h memory offset: 915h (for function 1 only) register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved intb#/ ri_out*/ pme# select 1 intb#/ ri_out*/ pme# select 0 r/w:000000 r/w:0 r/w:0 bit 1 bit 0 pin function 0 0 intb# or ri_out*, using existing cl-pd6832 select bits 0 1 do not program this value. 10 pme# as de?ned by pci speci?cation (pci power management add-on speci?cation) 1 1 do not program this value.
june 1998 147 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.5 gpio output control bits 3:0 gpio[4:1] output control when these bits are 0, the corresponding gpio pin is put into the high-impedance state. setting these bits causes the corresponding gpio output data bit to be driven onto the corresponding gpio pin. if the corresponding gpio input control bit is low, the output drives both active high and active low. if the corresponding gpio input control bit is high, the output is open-drain and drives low only. bits 7:4 reserved 11.7.6 gpio input control bits 3:0 gpio[4:1] input control when these bits are set to 0, the corresponding inputs are disabled and read back 1s. this is used to prevent ?oating inputs from drawing excessive power. when these bits are set, the data read from the gpio input data register re?ects the value on the corresponding pin. if enabled, a ?oating input can cause excessive power consumption, and can cause the other inputs to operate incorrectly. if the corresponding gpio output control bit is set, the pin is an output, regardless of the state of the gpio input control bit. bits 7:4 gpio[4:1] pull-up enable register name: gpio output control i/o index: 2fh extended index: 18h memory offset: 918h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gpio4 output control gpio3 output control gpio2 output control gpio1 output control r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 register name: gpio input control i/o index: 2fh extended index: 19h memory offset: 919h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpio4 pull-up enable gpio3 pull-up enable gpio2 pull-up enable gpio1 pull-up enable gpio4 input control gpio3 input control gpio2 input control gpio1 input control r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 gpio pin tristate or open-collector per register 918h and 919h. 1 gpio pin pull-up resistor to +5v pins supply, except when outputting 0.
advance data book v0.3 june 1998 148 extension registers cl-pd6833 pci-to-cardbus host adapter 11.7.7 gpio output data bits 3:0 gpio[4:1] output data when in the output mode, data written to this register is driven onto the corresponding gpio pin. this register reads back what was last written, regardless of the state of the gpio pins. bits 7:4 reserved 11.7.8 gpio input data bits 3:0 gpio[4:1] input data if the corresponding gpio output control and gpio input control bits are both low, this address reads back a 1. in any other case, this address reads the actual state of the gpio pins whether in input or output mode. in the output mode, the data read from a pin can be compared to the corresponding data bit in the gpio output data register to verify that there is not a problem with that output. bits 7:4 reserved register name: gpio output data i/o index: 2fh extended index: 1ah memory offset: 91ah register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gpio4 output data gpio3 output data gpio2 output data gpio1 output data r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 register name: gpio input data i/o index: 2fh extended index: 1bh memory offset: 91bh register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gpio4 input data gpio3 input data gpio2 input data gpio1 input data r/w:0 r:1 r:1 r:1 r:1
june 1998 149 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8 prefetch window register this register is read-only in the current version of the cl-pd6833. 11.8.1 pci space control bits 7:6, 4:0 gen map [6:0] pci type if the corresponding bit in the window type select register is set and the pci space control bit is reset, then the programmed general map window responds to pci memory operations. if the pci space control bit is set, then the programmed general map window responds to pci i/o operations. if the corresponding bit in the window type select register is reset, this bit is ignored. bit 5 reserved configuration register name: prefetch window register i/o index: 2fh extended index 1ch offset: 91ch register per: socket register compatibility type: ext. bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 3 (high) r/w:00000000 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 (low) r/w:00000000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 1 (high) r/w:00000000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 (low) r/w:00000000 register name: pci space control i/o index: 2fh extended index: 22h memory offset: 922h register per: socket register compatibility type: ext bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gen map 6 pci type gen map 5 pci type reserved gen map 4 pci type gen map 3 pci type gen map 2 pci type gen map 1 pci type gen map 0 pci type r/w:1 r/w:1 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 general map registers con?gured for pci memory operation. 1 general map registers con?gured for pci i/o operation.
advance data book v0.3 june 1998 150 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.2 pc card space control bits 7:6, 4:0 gen map [6:0] pc card type if the corresponding bit in the window type select register is set, and the pc card space control bit is reset, then accesses through this window are memory commands to the pc card. if the corresponding bit in the window type select register is set and the pc card space control bit is set, then accesses through this window are i/o commands to the pc card. if the corresponding bit in the window type select register is reset, this bit is ignored. bit 5 reserved 11.8.3 window type select bits 7:6, 4:0 gen map [6:0] type when these bits are set, the corresponding general windows are programmable with the pci space control and pc card space control registers. the controls for the window data size, timer select, and auto data size bits are programmed in the gen map extra control registers. when these bits are reset, the corresponding general map registers revert to their default con?guration. the controls for the window data size, timer select, and auto data size bits comes from the i/o window control, memory map start address high, and memory map end address high registers. bit 5 reserved register name: pc card space control i/o index: 2fh extended index: 23h memory offset: 923h register per: socket register compatibility type: ext bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gen map 6 pc card type gen map 5 pc card type reserved gen map 4 pc card type gen map 3 pc card type gen map 2 pc card type gen map 1 pc card type gen map 0 pc card type r/w:1 r/w:1 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 general map con?gured for pc card memory offset and commands. 1 general map con?gured for pc card i/o offset and commands. register name: window type select i/o index: 2fh extended index: 24h memory offset: 924h register per: socket register compatibility type: ext bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gen map 6 type gen map 5 type reserved gen map 4 type gen map 3 type gen map 2 type gen map 1 type gen map 0 type r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:0 0 general map registers con?gured for default operation. 1 general map registers con?gured for programmable operation.
june 1998 151 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.4 misc control 3 note: bits 3:0 are part of the pme_cxt (pme context), a set of bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 3:0 are con?guration switches loaded during a power-on reset or hardware reset. the con?guration values determine the type of serial interrupt protocol and the type of serial socket power control to be used. the con?guration values are to be preset using pull-down resistors or a pull-up resistor. these bits can also be loaded through a register write. bits 3:0 are connected to the pads as follows: bits 1:0 system interrupt signalling mode a during power-on reset or hardware reset, bit 5 should be written to 0. b bit 3 is 0 if the last pci_rst was during power-up and 1 if the last pci_rst was a bus segment reset with power-on. c during power-on reset or hardware reset, bit 2 is loaded with value of the slatch/smbclk pin (130). d during power-on reset or hardware reset, bits 0 and 1 are ?lled from information provided on led_out*/hw_suspend# (133) and spkr_out* (128) from table 11-3 . register name: misc control 3 i/o index: 2fh extended index: 25h memory offset: 925h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 multimedia arm reserved hardware suspend enable reserved socket power- control interface signalling mode system interrupt signalling mode r/w:0 r/w:0 r/w:0 a r/w:0 r/w: power-on reset b r/w:0 c r/w:00 d table 11-3. interrupt signalling power-on settings settings misc control 3 bit 1 misc control 3 bit 0 irq15 sin# pci 1 1 open pull-up pci/way 1 0 pull-down pull-down pc/pci 0 0 pull-down pull-up external-hardware 0 1 open pull-down bit 1 bit 0 interrupt signalling mode 00 pc/pci interrupt signalling mode. requires systems supporting sic (serial interrupt controller). 0 1 external-hardware interrupt signalling mode. 1 0 pci/way serial format. 1 1 pci interrupt signalling mode.
advance data book v0.3 june 1998 152 extension registers cl-pd6833 pci-to-cardbus host adapter the cl-pd6833 supports four interrupt signalling modes: pci interrupt signalling mode, pc/pci interrupt signalling mode, external-hardware interrupt signalling mode, and the pci/way serial format. when con?gured for external-hardware interrupt signalling, pins 205 and 206 are used as the isld and isdat signals to the external cl-pd6701 that provides eight parallel irq lines, pin 203 is inta#, and pin 204 is intb#/ri_out*. refer to the application note interrupt signalling modes for the cl-pd6730 and cl-pd6832 (an-pd8). when con?gured for the pci/way interrupt signalling mode, pin 205 works as the irqser bidirectional interrupt line. pin 203 works as inta# and pin 204 works as intb#/ri_out*. pin 206 is not used. this is the only mode in which pin 203 works as an led indicator for socket 0 and pin 205 works as a led indicator for socket 1. refer to the misc. control 5 register at extended index 30h (memory offset 930h). bit 2 socket power-control interface signalling mode when this bit is 0, the tis tps2206 serial interface protocol is enabled. this interface uses three pins: sclk, sdata, and slatch. sclk is the reference clock to the cl-pd6833. the power control data is sent to tis tps2206 over the sdata pin and latch signal over the slatch pin. when this bit is 1, the intel smbus protocol is supported. this interface uses two pins, namely smbdata and smbclk. the reference clock of 32 khz is fed through the sclk pin and is required during suspend (both hardware and software). the power control data is sent serially over smbdata (bidirectional) and clock over smbclk. this interface is used by max1601 dual- socket power control chip (serial version) when bit 5 of this register is 0. when bit 5 is 1, the new smbus protocol is used and status read back is available. bit 3 reserved this bit is 0 if the last pci_rst was during power-up, and 1 if the last pci_rst was a bus segment reset with power-on. bit 4 hardware suspend enable bits 6:5 reserved bit 7 multimedia arm no multimedia operation can occur without setting this bit to 1; the bit provides an overriding control mechanism. the multimedia arm bit ensures that multimedia operation is not inadvertently set by software or point enablers. this bit also controls the output drivers of the zv port. see the multimedia enable bit 0 (in section 11.1 on page 132 ). this bit must be set to 0 with bit 0 of index 16h. 0 tis tps2206 serial signalling mode (uses 3 pins, supports two sockets) or cl-pd6701 serial signalling mode (currently uses tis tps2206 serial protocol) 1 system management bus signalling mode (uses 2 pins, supports two sockets) 0 normal operation 1 device goes into hardware suspend if the suspend# pin (133) is low. 0 multimedia arm disabled. zv port pins (connected to vga zv port) are high-impedance. 1 multimedia arm enabled. zv port pins (connected to vga zv port) are enabled.
june 1998 153 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.5 smbus socket power control ad dress pme_cxt note: pme_cxt (pme context) is a set of register bits that do not get reset or initialized if pme enable is true when the cl-pd6833 changes power states from d3 to d0 through a software pci bus segment reset. bits 1:0 reserved bits 7:2 smbus socket power control address a[6:1] this register contains the most-signi?cant six bits of the smbus (system management bus) slave address for the socket power-control device. the smbus speci?cation for the slave address for a pc card socket power control device is 101000xx. this register resets to 101000 for bits 7:2, and the socket power control device can be hard con?gured to this address to eliminate additional software setup. the cl-pd6833 supports the max1601, which is a dual-socket power control chip employing the smbus protocol (see also the register misc control 3 on page151 ). register name: smbus socket power control address pme_cxt i/o index: 2fh extended index: 26h memory offset: 926h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a6 a5 a4 a3 a2 a1 reserved r/w:1 r/w:0 r/w:1 r/w:0 r/w:0 r/w:0 r/w:00
advance data book v0.3 june 1998 154 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.6 gen map 0C6 extra control (i/o) bit 0 extra i/o window size when bit 1 of this register is 0, this bit determines the width of the data path for gen map i/o window accesses to the card. when bit 1 is 1, this bit is ignored. bit 1 extra auto-size i/o window this bit determines the width of the data path for gen map i/o window accesses to the card. note that when this bit is 1, the iois16# signal determines the width of the data path to the card. bit 2 reserved bit 3 extra timing register select this bit determines the access timing speci?cation for gen map i/o window. bits 7:4 reserved register name: gen map 0C6 extra control (i/o) i/o index: 2fh extended index : 27hC2dh memory offset: 927hC92dh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved extra timing register select reserved extra auto-size i/o window extra i/o window size r:0000 r/w:0 r/w:0 r/w:0 r/w:0 0 8-bit data path to gen map i/o window. 1 16-bit data path to gen map i/o window. 0 gen map i/o window size (see bit 0 of this register) determines the data path for gen map i/o window accesses. 1 the data path to gen map i/o window is determined by the iois16# level returned by the card. 0 accesses made with timing speci?ed in timer set 0 registers. 1 accesses made with timing speci?ed in timer set 1 registers.
june 1998 155 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.7 gen map 0C6 extra control (memory) when the window type select register bit corresponding to a general map register is set (and that window is con?gured in pc card space control as memory), this register is used to program the memory behavior to the pc card socket. when the window type select register bit is reset, this register is ignored. when the window type select register bit is set and the pc card space control register bit is set to 0 (indi- cating memory operation), this register is con?gured as follows. bit 0 extra window data size bit 1 reserved bits 3:2 extra card timer select this ?eld selects the timer set. timer set 0 and 1 reset to values compatible with standard pci and three-wait-state cycles. bits 7:4 reserved register name: gen map 0C6 extra control (memory) i/o index: 2fh extended index : 27hC2dh memory offset: 927hC92dh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved extra card timer select reserved extra window data size r:0000 r/w:00 r/w:0 r/w:0 0 8-bit data path to pc card. 1 16-bit data path to pc card. bit 3 bit 2 timer set select 0 0 selects timer set 0 0 1 selects timer set 1 1 0 selects timer set 1 1 1 selects timer set 1
advance data book v0.3 june 1998 156 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.8 extension card status change this register indicates the source of a management interrupt generated by the cl-pd6833. note: the corresponding bit in the management interrupt con?guration register must be set to 1 to enable each speci?c status change detection. this register can only be cleared after accessing register 804h, and writing a 1 to the corresponding bit in register 92eh. bit 0 battery dead or status change in memory card interface mode, this bit is set to 1 when the bvd1/stschg#/ri# pin (see page 20 ) changes from high to low, indicating a battery dead condition. in i/o card interface mode, this bit is set to 1 when the bvd1/stschg#/ri# pin changes from either high to low or low to high. in i/o card interface mode, the function of this bit is not affected by bit 7 of the interrupt and general control register. this bit is reset to a 0 if the card status register is ?rst cleared and then a 1 is written to this bit. bit 1 battery warning change in memory card interface mode, this bit is set to 1 when the bvd2/spkr#/led# pin changes from high to low, indicating a battery warning. this bit is not valid in i/o card interface mode. this bit is reset to a 0 if the card status register is ?rst cleared and then a 1 is written to this bit. bit 2 ready change this bit is 1 when a change has occurred on the rdy/ireq# pin. this bit is reset to a 0 if the card status register is ?rst cleared and then a 1 is written to this bit. register name: extension card status change i/o index: 2fh extended index: 2eh memory offset: 92eh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved (latched) card detect change (latched) ready change (latched) battery warning change (latched) battery dead or status change r:0 r:0 r:0 r:0 r/c:0 r/c:0 r/c:0 r/c:0 0 a transition (from high to low in memory card interface mode or either high to low or low to high in i/o card interface mode) on the bvd1/stschg#/ri# pin has not occurred since this register was last read. 1 a transition on the bvd1/stschg#/ri# pin has occurred. 0 a transition (from high to low) on the bvd2/spkr#/led# pin has not occurred since this register was last read. 1 a transition on the bvd2/spkr#/led# pin has occurred. 0 a transition on the rdy/ireq# pin has not occurred since this register was last read. 1 a transition on the rdy/ireq# pin has occurred.
june 1998 157 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter bit 3 card detect change this bit is set to 1 when a change has occurred on the cd1# or cd2# pin. this bit is reset to a 0 if the card status register is ?rst cleared and then a 1 is written to this bit. bits 7:4 reserved 11.8.9 misc control 4 bits 1:0 socket clock divide control these bits control the clock rate to the sockets and are a binary divide of the pci input clock. bit 2 slot active this bit is reset to 0 by rst# and by any read of this register. when the pc card is accessed for write or read, this bit is set. this bit can be used to monitor the traf?c ?ow of a card. by reading this bit during a periodic interrupt, a pro?le of the card activity can be established for power management. bits 7:3 reserved 0 a transition on neither the cd1# nor the cd2# pin has occurred since this register was last read. 1 a transition on either the cd1# or the cd2# pin or both has occurred. register name: misc control 4 i/o index: 2fh extended index: 2fh memory offset: 92fh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved slot active socket clock divide control r:0 r:0 r:0 r:0 r:0 r:0 r/w:00
advance data book v0.3 june 1998 158 extension registers cl-pd6833 pci-to-cardbus host adapter 11.8.10 misc control 5 bit 0 dual led enable when this bit is set to 1, pin 203 works as an active-low led output for socket 0 activity. pin 206 works as an active-low led output for socket 1 activity. this feature is available only in the pci/way interrupt signalling mode. refer to the misc control 3 register on page 151 . bits 7:1 reserved 11.8.11 misc control 6 bits 3:0 reserved bit 4 5-v socket this bit sets the 5-v socket bit in the present state register. writing 1 sets this bit in the present state register, and writing 0 clears bit in the present state register. bit 5 3.3-v socket this bit sets the 3.3-v socket bit in the present state register. writing 1 sets this bit in the present state register, and writing 0 clears bit in the present state register. bit 6 x-v socket this bit sets the x-v socket bit in the present state register. writing 1 sets this bit in the present state register, and writing 0 clears bit in the present state register. bit 7 y-v socket this bit sets the y-v socket bit in the present state register. writing 1 sets this bit in the present state register, and writing 0 clears bit in the present state register. register name: misc control 5 i/o index: 2fh extended index: 30h memory offset: 930h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dual led enable r:0000000 r/w:0 register name: misc control 6 i/o index: 2fh extended index: 31h memory offset: 931h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y-v socket x-v socket 3.3-v socket 5-v socket reserved w:0 w:0 w:1 w:1 r:0000
june 1998 159 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9 device identi?cation and implementation scheme there are four-byte-wide registers with read-only device information, and four-byte-wide read/write regis- ters that contain speci?c system implementation information. determining this register exists if bits 4:1 of the chip information register (memory offset 81fh) read back 0h, the chip information is contained in bits 3:0 of the mask revision register (memory offset 934h). 11.9.1 mask revision byte bits 3:0 mask revision these bits indicate the mask revision of the device. the binary value is interpreted as in the following table: bits 7:4 rfu (reserved for future use) register name: mask revision byte i/o index: 34h memory offset: 934h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfu mask revision r:0 r:0 r:0 r:0 r:0 r:0 r:0 r:0 bits 3:0 mask revision 0h a 1h b 2h c 3h d 4h e 5h f 6h g 7h h 8h j 9h k ah l bh m ch n dh p eh q fh r
advance data book v0.3 june 1998 160 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.2 product id byte bits 11:8 product code these bits indicate the product code of the device within its family. product codes cl-pd6833 family bits 15:12 family code a value of 04h indicates the cl-pd683x family. register name: product id byte i/o index: 35h memory offset: 935h register per: chip register compatibility type: ext. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 family code product code r:0 r:1 r:0 r:0 r:0 r:0 r:0 r:1 0h cl-pd6833 pci/cardbus controller, dual isolated sockets, 208-pin mqfp or lqfp. 2hCfh reserved for future use for the cl-pd683x devices.
june 1998 161 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.3 device capability byte a bits 17:16 # sockets [1:0] (number of sockets supportable by device) this bit ?eld indicates how many sockets a device is capable of supporting, expressed as the highest socket index number supportable, for example 00 indicates only socket 0 is supportable, meaning a single socket device, and 11 indicates sockets 3 through 0 are supportable, indicating a four-socket capable device. bit 18 ide interface a value of 0 indicates that the cl-pd6833 does not support driving an external ide drive. bit 19 slave dma a 1 at this bit indicates that the cl-pd6833 can act as a dma slave. the slave dma wired bit (bit 2 of the device implementation byte a register; see page 163 ) indicates whether a system is wired to allow this feature to be used. bit 20 rfu (reserved for future use) bit 21 gpstb capable a value of 0 in this ?eld indicates that the cl-pd6833 does not support general-purpose strobe. bit 22 rfu (reserved for future use) bit 23 per-socket led if this bit is set to 1, the device is capable of supporting independent leds on each socket. if this bit is set to 1, it is intended that socket services would check bits 16 and 17 of the device implementation byte c register (see page 165 ) to determine if per-socket leds are supported in the system implementation. the description of bits 16 and 17 explains the software implications if per-socket led support is to be enabled. register name: device capability byte a i/o index: 36h memory offset: 936h register per: chip register compatibility type: ext. bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 per-socket led rfu gpstb capable rfu slave dma ide interface # sockets 1 # sockets 0 r:1 r:0 r:0 r:0 r:1 r:0 r:0 r:1
advance data book v0.3 june 1998 162 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.4 device capability byte b bit 24 cardbus capable a 1 in this bit indicates that the cl-pd6833 is capable of supporting pc card 32 (cardbus) cards. bit 25 lock# support a 1 indicates that the cl-pd6833 is capable of supporting operations involving the lock# signal. note that bit 25 of the device implementation byte d register must be referenced to determine whether lock# is a supported signal in the system implementation. bit 26 clkrun# support a 1 indicates that the cl-pd6833 is capable of supporting pci mobile speci?cation clkrun# signalling for control of system clock turn on/turn off. note that the least-signi?cant bit of the device implementation byte d register must be referenced to determine whether this feature is supported in the system implementation. bits 30:27 rfu (reserved for future use) bit 31 extended definitions a 0 indicates that there is no extended de?nition. register name: device capability byte b i/o index: 37h memory offset: 937h register per: chip register compatibility type: ext. bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 extended definitions rfu (zv) rfu (cb) clkrun# support lock# support cardbus capable r:0 r:0 r:0 r:1 r:1 r:1
june 1998 163 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.5 device implementation byte a all bits of this byte are read/write. device reset defaults are speci?c to each device. a bios write to this byte before bringing of socket services sets these bits to re?ect which of these features are supported in the system implementation. bit 0 sockets present 0 bit 1 sockets present 1 bits 1:0 indicate the socket features supported in the system implementation. bit 2 slave dma wired this bit indicates whether the system is wired to allow the slave dma feature to be used. bit 3 vs1/vs2 wired when this bit is 1, the system is wired to use the vs1/vs2 pin. when this bit is 0 the system is not wired and is not capable of using the vs1/vs2 pin. bits 5:4 gpstb [b:a] wired bits 5:4 indicate the general-purpose strobe features supported in the system implementation. bit 6 hardware suspend wired a 1 indicates that a pin on the device designated as a hardware control of suspend for deep power saving has been connected to system circuitry designed for power management. bit 7 ri_out wired a 1 indicates that a pin on the device designated as ri_out has been connected to ring indicate circuitry. socket services must set the misc. control 2 register (i/o index 1e) bit 7 to a 1, thereby enabling this alternate pin de?nition as it has been wired. a value of 1 implies that the ri_out*/intb# pin is not connected to the pci bus intb# line, but is instead connected to an smi type system function designed to wake up a system on modem ring. register name: device implementation byte a i/o index: 38h memory offset: 938h register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ri_out wired hardware suspend wired gpstb b wired gpstb a wired vs1/vs2 wired slave dma wired sockets present 1 sockets present 0 r/w:0 r/w:0 r/w:0 r/w:0 r/w:1 r/w:0 r/w:0 r/w:1
advance data book v0.3 june 1998 164 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.6 device implementation byte b bit 8 3.3-v v cc capable a value of 1 indicates that 3.3-v voltage source is available in this system. a value of 0 indicates that 3.3-v voltage source is not available in this system. bit 9 5.0-v v cc capable a value of 1 indicates that 5.0-v voltage source is available in this system. a value of 0 indicates that 5.0-v voltage source is not available in this system. bit 10 y-v capable a value of 1 indicates that y.y-v voltage source is available in this system. a value of 0 indicates that y.y-v voltage source is not available in this system. bit 11 x-v capable a value of 1 indicates that x.x-v voltage source is available in this system. a value of 0 indicates that x.x-v voltage source is not available in this system. bit 12 vpp 12 v available a value of 1 indicates that a vpp of 12 v is supported in this system. a value of 0 indicates that a vpp of 12 v is not supported in this system. bit 13 vpp_vcc 1a a value of 1 indicates that the socket can deliver 1 a at v pp = v cc . bit 14 rf rated sockets a value of 1 indicates that the sockets in this system are designed to handle cards that operate at radio frequencies like cellular fax/modem and pagers. a value of 0 indicates that the sockets in this system are not designed to handle cards that operate at radio frequencies like cellular fax/modem and pagers. bit 15 rfu (reserved for future use) register name: device implementation byte b i/o index: 39h memory offset: 939h register per: chip register compatibility type: ext. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 rfu rf rated sockets vpp_ vcc 1a vpp 12 v available x-v capable y-v capable 5.0-v v cc capable 3.3-v v cc capable r/w:0 r/w:1 r/w:0 r/w:1 r/w:0 r/w:0 r/w:1 r/w:1
june 1998 165 advance data book v0.3 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.7 device implementation byte c bit 16 led wired a value of 1 indicates that a single activity socket led is available for both sockets. a value of 0 indicates that a single activity socket led is not available for both sockets. bit 17 per-socket led a value of 1 indicates that an activity socket led is available on each socket and is controlled through extended index 930h. a value of 0 indicates an activity socket led is not available on each socket and is not controlled through extended index 930h. bit 18 spkr wired a value of 1 indicates that a speaker is connected to the sockets. a value of 0 indicates that a speaker is not connected to the sockets. bit 19 zv port a wired a value of 1 indicates that socket a is wired for zv operation. a value of 0 indicates that socket a is not wired for zv operation. bit 20 zv port b wired a value of 1 indicates that socket b is wired for zv operation. a value of 0 indicates that socket b is not wired for zv operation. bits 23:21 rfu (reserved for future use) register name: device implementation byte c i/o index: 3ah memory offset: 93ah register per: chip register compatibility type: ext. bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 rfu rfu (zv) zv port b wired zv port a wired spkr wired per-socket led led wired r/w:0 r/w:0 r/w:1 r/w:1 r/w:1 r/w:0 r/w:0
advance data book v0.3 june 1998 166 extension registers cl-pd6833 pci-to-cardbus host adapter 11.9.8 device implementation byte d bit 24 clkrun# wired a value of 1 indicates that the system supports clkrun# protocol. a value of 0 indicates that the system does not support clkrun# protocol. bit 25 lock# wired a value of 1 indicates that the system supports a lock#. a value of 0 indicates that the system does not support a lock#. bits 29:26 rfu (reserved for future use) bit 30 clk option wired a value of 1 indicates that an external clock is available to the cl-pd6833. a value of 0 indicates that an external clock is not available to the cl-pd6833. bit 31 rfu (reserved for future use) register name: device implementation byte d i/o index: 3bh memory offset: 93bh register per: chip register compatibility type: ext. bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 rfu clk option wired rfu lock# wired clkrun# wired r/w:0 r/w:0 r/w:0 r/w:1 r/w:1
june 1998 167 advance data book v0.3 timing registers cl-pd6833 pci-to-cardbus host adapter 12. timing registers the following information about the timing registers is important: l all timing registers take effect immediately and should only be changed when the fifo is empty (see the fifo control register on page 134 ). l selection of timer set 0 or timer set 1 register sets is controlled by i/o window control bits 3 and 7. 12.1 setup timing 0C1 there are two separate setup timing registers, each with identical ?elds. these registers are located at the following indexes: index (socket a) setup timing 3ah setup timing 0 3dh setup timing 1 the setup timing register for each timer set controls how long a pc card cycles command (that is, oe#, we#, iord#, iowr#; see table 2-2 on page 15 ) setup time is, in terms of the number of internal clock cycles. the overall command setup timing length s is programmed by selecting a value (bits 5:0) to produce the overall command setup timing length according to the following formula: s = n val + 1 equation 12-1 the value of s , representing the number of clock cycles for command setup, is then multiplied by the clock period to determine the actual command setup time (see section 15.3.3 for further discussion). bits 5:0 setup multiplier value this ?eld indicates an integer value n val from 0 to 63 to control the length of setup time before a command becomes active. bits 7:6 reserved table 12-1. timing registers quick reference register name i/o index memory offset page number setup timing 0C1 3ah, 3dh 83ah, 83dh 167 command timing 0C1 3bh, 3eh 83bh, 83eh 168 recovery timing 0C1 3ch, 3fh 83ch, 83fh 169 register name: setup timing 0C1 i/o index: 3ah, 3dh memory offset: 83ah, 83dh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved setup multiplier value r:00 r/w:000000/000011
advance data book v0.3 june 1998 168 timing registers cl-pd6833 pci-to-cardbus host adapter 12.2 command timing 0C1 there are two separate command timing registers, each with identical ?elds. these registers are located at the following indexes: i/o index memory offset command timing (socket a) 3bh 83bh command timing 0 3eh 83eh command timing 1 the command timing register for each timer set controls how long a pc card cycles command (that is, oe#, we#, iord#, iowr#; see table 2-2 on page 15 ) active time is, in terms of the number of internal clock cycles. the overall command timing length c is programmed by selecting a multiplier value (bits 5:0) to produce the overall command timing length according to the following formula: c = n val + 1 equation 12-2 the value of c , representing the number of clock cycles for a command, is then multiplied by the clock period to determine the actual command active time (see section 15.3.3 for further discussion). bits 5:0 command multiplier value this ?eld indicates an integer value n val from 0 to 63; it controls the length that a command is active. bits 7:6 reserved register name: command timing 0C1 i/o index: 3bh, 3eh memory offset: 83bh, 83eh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved command multiplier value r:00 r/w:000111/010001
june 1998 169 advance data book v0.3 timing registers cl-pd6833 pci-to-cardbus host adapter 12.3 recovery timing 0C1 there are two separate recovery timing registers, each with identical ?elds. these registers are located at the following indexes: i/o index memory offset recovery timing (socket a) 3ch 83ch recovery timing 0 3fh 83fh recovery timing 1 the recovery timing register for each timer set controls how long a pc card cycles command (that is, oe#, we#, iord#, iowr#; see table 2-2 on page 15 ) recovery time is, in terms of the number of internal clock cycles. the overall command recovery timing length r is programmed by selecting a multiplier value (bits 5:0) to produce the overall command recovery timing length according to the following formula: r = n val + 1 equation 12-3 the value of r , representing the number of clock cycles for command recovery, is then multiplied by the clock period to determine the actual command recovery time (see section 15.3.3 for further discussion). bits 5:0 recovery multiplier value this ?eld indicates an integer value n val from 0 to 63; it controls the length of recovery time after a command is active. bits 7:6 reserved register name: recovery timing 0C1 i/o index: 3ch, 3fh memory offset: 83ch, 83fh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved recovery multiplier value r:00 r/w:000100/000100
advance data book v0.3 june 1998 170 timing registers cl-pd6833 pci-to-cardbus host adapter notes
june 1998 171 advance data book v0.3 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13. dma operation registers this chapter discusses the dma registers used to make pci/way dma operate. all registers in this chapter are i/o registers offset from the dma slave con?guration register. bits 31:4 of this register make up the dma base address used for all of these registers. the registers in this chapter are derived from the intel 8237 register set. table 13-1. dma operation registers quick reference register name dma base address offset page number low address 0h 172 mid low address 1h 172 mid high address 2h 173 high address 3h 173 low count 4h 174 mid count 5h 174 high count 6h 174 dma command and status 8h 175 request register 9h 176 mode register bh 177 master clear dh 178 mask register fh 178
advance data book v0.3 june 1998 172 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.1 low address this register is used to form part of the address for dma transfers. this register corresponds to the base and current address register of the intel 8237 for write operations. for read operations this register contains the current address. bits 7:0 low address when bits 2:1 of the dma slave con?guration register indicate that an 8-bit transfer is to occur, this register contains the starting address bits 7:0. if bits 2:1 of the dma slave con?guration register indicate that a 16-bit transfer is to occur, then this register contains starting address bits 8:1 and address 0 is always 0 at the pc card. 13.2 mid low address this register is used to form part of the address for dma transfers. bits 7:0 mid low address this register corresponds to the base and current address register of the intel 8237 for write operations. for read operations this register contains the current address. when bits 2:1 of the dma slave con?guration register indicate that an 8-bit transfer is to occur, this register contains the starting address bits 15:8. if bits 2:1 of the dma slave con?guration register indicate that a 16-bit transfer is to occur, then this register contains the starting address bits 16:9. register name: low address i/o index: 0h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 low address 8 bit 7:0 16 bit 8:1 r/w:00000000 register name: mid low address i/o index: 1h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mid low address 8 bit 15:8 16 bit 16:9 r/w:00000000
june 1998 173 advance data book v0.3 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.3 mid high address this register is used to form part of the address for dma transfers. bits 7:0 mid high address this register corresponds to the base and current address register of the intel 8237 for write operations. for read operations this register contains the current address. when bits 2:1 of the dma slave con?guration register indicate that an 8-bit transfer is to occur, this register contains the starting address bits 23:16. if bits 2:1 of the dma slave con?guration register indicate that a 16-bit transfer is to occur, then this register contains low address bits 23:17, and bit 0 of this register is not used. 13.4 high address this register is used to form part of the address for dma transfers. this register is only employed to indicate the memory address of the dma transfer when bit 3 of the dma slave con?guration is set to a 1. bits 7:0 high address this register corresponds to the base and current address register of the intel 8237 for write operations. for read operations this register contains the current address. this register contains the starting address bits 31:24. this register is enabled by bit 3 of the dma slave con?guration register. if bit 3 of the dma slave con?guration is reset, then address bits 31:24 are 00 during dma transfers from the cl-pd6833 to memory. register name: mid high address i/o index: 2h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mid high address 8 bit 23:16 16 bit 23:17 r/w:00000000 register name: high address i/o index: 3h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high address 8 bit 31:24 16 bit 31:24 r/w:00000000
advance data book v0.3 june 1998 174 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.5 low count this register is used to form part of the count for dma transfers. bits 7:0 low count this register corresponds to the base and current word count of the intel 8237 register set. dma transfers are counted by transaction, not by byte, word, or doubleword. the count registers count down from the programmed value to zero and then one more. when written, this register is the total count of transactions plus one. when read, this register re?ects the remaining transactions. 13.6 mid count this register is used to form part of the count for dma transfers. bits 7:0 mid count 13.7 high count this register is used to form part of the count for dma transfers when bit 3 of the dma slave con?guration register is set. when that bit is not set, this register is not used. bits 7:0 high count when enabled this register can be used to increase the total number of transfers above the original 64-kbyte transfers of the original intel 8237. register name: low count i/o index: 4h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 low count 7:0 r/w:00000000 register name: mid count i/o index: 5h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mid count 15:8 r/w:00000000 register name: high count i/o index: 6h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high count 23:16 r/w:00000000
june 1998 175 advance data book v0.3 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.8 dma command and status bit 0 mem-to-mem enable reads from this bit return terminal count. bit 1 address hold enable reads from this bit return terminal count. bit 2 controller disable this bit disables dma transfers. reads from this bit return terminal count. bit 3 compressed timing reads from this bit return terminal count. bit 4 rotating priority reads from this bit return the state of the pc card dma request line inverted. bit 5 extended write select reads from this bit return the state of the pc card dma request line inverted. bit 6 dreq sense reads from this bit return the state of the pc card dma request line inverted. bit 7 dack sense reads from this bit return the state of the pc card dma request line inverted. register name: dma command and status i/o index: 8h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dack sense dreq sense extended write select rotating priority compressed timing controller disable address hold enable mem-to-mem enable r:0 r:0 r:0 r:0 r/w:0 r:0 r:0 r/w:0
advance data book v0.3 june 1998 176 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.9 request register this register is similar to the request register of the intel 8237. reads from this register are unde?ned and only the set request bit has any meaning for this implementation. bits 1:0 reserved bit 2 set request if the transfer mode bits are set to do block transfers, this bit initiates transfers with no hardware request present on the pc card interface. bits 7:3 reserved register name: request register i/o index: 9h register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set request reserved r:00000 w:0 r:00
june 1998 177 advance data book v0.3 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.10 mode register this register emulates the mode register of the intel 8237. unlike the intel 8237 mode register, this register is readable. bits 1:0 channel number (ignored) writes to these bits have no effect. these bits read back what was written to them. bits 3:2 transfer mode these two bits determine the transfer mode to be used. bit 4 autoinitialize this bit puts the dma controller in auto-initialize mode. in this mode the current address and count registers are reloaded from the base registers. this sets the dma controller for a new transfer at the end of the current transfer. bit 5 address decrement if this bit is set the addresses generated proceed downward from the base address until the count is exhausted. if this bit is reset, the addresses generated increment until the end of transfer. bits 7:6 request mode these two bits determine the request mode to be used. register name: mode register i/o index: bh register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 request mode address decrement autoinitialize transfer mode channel number (ignored) r/w:00 r/w:0 r/w:0 r/w:00 r/w:00 bit 3 bit 2 transfer mode 0 0 verify mode 0 1 dma write 1 0 dma read 1 1 reserved bit 7 bit 6 request mode 0 0 demand mode 0 1 single transfer mode 1 0 block mode select 1 1 cascade mode (not implemented)
advance data book v0.3 june 1998 178 dma operation registers cl-pd6833 pci-to-cardbus host adapter 13.11 master clear bits 7:0 master clear this register emulates the master clear register of the intel 8237. unlike the intel 8237, there is no temporary register to read back, so read back is not supported. when this register is written, the dma section of the cl-pd6833 assumes the same state as caused by pci_rst. the dma slave con?guration register is unaffected by writes to this register. 13.12 mask register this register emulates the mask registers of the intel 8237. unlike the intel 8237, there is only one channel represented here. read back is supported. bit 0 mask when this bit is 1, the dreq from the pc card is ignored. when this bit is 0, dma requests are enabled. this bit is automatically set if the autoinitialize bit is not set when a transfer completes. bits 7:1 reserved register name: master clear i/o index: dh register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 master clear r/w:0 register name: mask register i/o index: fh register per: socket register compatibility type: dma bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mask r/w:0 r/w:0
june 1998 179 advance data book v0.3 ata mode operation cl-pd6833 pci-to-cardbus host adapter 14. ata mode operation the cl-pd6833 card interfaces can be dynamically con?gured to support a pc cardCcompatible ata disk interface (commonly known as ide) instead of the standard pc card interface. disk drives that can be made mechanically-compatible with pc card dimensions can thus operate through the socket using the ata electrical interface. con?guring a socket to support ata operation changes the function of certain card socket signals to sup- port the needs of the ata disk interface. table 14-1 lists each interface pin and its function when a cl-pd6833 card socket is operating in ata mode. refer to the cirrus logic application note con?guring pcmcia sockets for ata drive interface (an-pd5) for more information. all register functions of the cl-pd6833 are available in ata mode, including socket power control, inter- face signal disabling, and card window control. no memory operations are allowed in ata mode. note: general windows 5 and 6 must be used for proper ata operation. table 14-1. ata pin cross-reference pc card socket pin number function pc card interface ata interface 1 ground ground 2d3 d3 3d4 d4 4d5 d5 5d6 d6 6d7 d7 7 -ce1 -cs0 8 a10 n/c 9 -oe -ata (always low) 10 a11 n/c 11 a9 cs1* 12 a8 n/c 13 a13 n/c 14 a14 n/c 15 -we n/c 16 -ireq ireq 17 vcc vcc 18 vpp1 n/c 19 a16 n/c 20 a15 n/c 21 a12 n/c 22 a7 n/c 23 a6 n/c 24 a5 n/c 25 a4 n/c 26 a3 n/c 27 a2 a2 28 a1 a1 29 a0 a0 30 d0 d0 31 d1 d1 32 d2 d2 33 -iois16 -iocs16 34 ground ground table 14-1. ata pin cross-reference (cont.) pc card socket pin number function pc card interface ata interface
advance data book v0.3 june 1998 180 ata mode operation cl-pd6833 pci-to-cardbus host adapter 35 ground ground 36 -cd1 -cd1 37 d11 d11 38 d12 d12 39 d13 d13 40 d14 d14 41 d15 d15 42 -ce2 -cs1 43 vs1 vs1 44 -iord -iord 45 -iowr -iowr 46 a17 n/c 47 a18 n/c 48 a19 n/c 49 a20 n/c 50 a21 n/c 51 vcc vcc table 14-1. ata pin cross-reference (cont.) pc card socket pin number function pc card interface ata interface 52 vpp2 n/c 53 a22 n/c 54 a23 vu 55 a24 -m/s 56 a25 csel 57 vs2 vs2 58 reset reset* 59 -wait iochrdy 60 -inpack dreq 61 -reg -dack 62 -spkr -led 63 -stschg -pdiag 64 d8 d8 65 d9 d9 66 d10 d10 67 -cd2 -cd2 68 ground ground table 14-1. ata pin cross-reference (cont.) pc card socket pin number function pc card interface ata interface
june 1998 181 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15. electrical specifications 15.1 absolute maximum ratings 15.2 dc speci?cations a stresses above those listed may cause permanent damage to system components. these are stress ratings only; functional operation at these or any conditions above those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect system reliability. description absolute maximum rating a ambient temperature under bias 0 c to 70 c storage temperature - 65 c to 150 c voltage on any pin (with respect to ground) - 0.3 v to 0.3 v greater than the voltage of the +5v pin, respective to ground operating power dissipation 750 mw power dissipation during suspend mode 10 mw power supply voltage 7 v a injection current (latch up) 25 ma a table 15-1. general dc speci?cations symbol parameter min max unit conditions c in input capacitance 10.0 pf c out output capacitance 10.0 pf i il input leakage - 10.0 10.0 m a 0 < v in < respective v cc supply pin i pu internal pull-up current - 30 - 400 m a
advance data book v0.3 june 1998 182 electrical specifications cl-pd6833 pci-to-cardbus host adapter table 15-2. pc card (pcmcia) bus interface dc speci?cations symbol parameter min max unit conditions socket_vcc 5v power supply voltage 4.5 5.5 v normal operation socket_vcc 3v 3.0 3.6 v v ih input high voltage 2.0 v v dd core voltage = 3.0 v v il input low voltage 0.8 v v dd core voltage = 3.6 v v oh output high voltage 2.4 v at rated i oh , respective socket_vcc = 3.0 v v ohc output high voltage cmos socket_vcc C 0.5 v at rated i ohc , respective socket_vcc = 3.0 v v ol output low voltage 0.4 v at rated i ol i oh output high current - 2ma respective socket_vcc = 3.0 v, v oh = 2.4 v i ohc output high current cmos - 1ma respective socket_vcc = 3.0 v, v ohc = socket_vcc C 0.5 v i ol output low current 2ma respective socket_vcc = 3.0 v, v ol = 0.4 v
june 1998 183 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter a when core_vdd is 3.3 v, input thresholds are ttl-compatible; when core_vdd is 5 v, input thresholds are cmos-compatible. table 15-3. pci bus interface dc speci?cations symbol parameter min max unit conditions pci_vcc 5v power supply voltage 4.5 5.5 v normal operation pci_vcc 3v 3.0 3.6 v v ih a input high voltage 2.0 v v dd core voltage = 3.0 v v il a input low voltage 0.8 v v dd core voltage = 3.6 v v oh output high voltage 2.4 v at rated i oh , pci_vcc = 3.0 v v ohc output high voltage cmos pci_vcc C 0.5 v at rated i ohc , pci_vcc = 3.0 v v ol output low voltage 0.5 v at rated i ol i oh output current high - 5ma pci_vcc = 3.0 v, v oh = 2.4 v i ohc output current high cmos - 1ma pci_vcc = 3.0 v, v ohc = pci_vcc C 0.5 v i ol output current low 16 ma pci_vcc = 3.0 v, v ol = 0.5 v table 15-4. general i/o pin dc speci?cations for 2-, 4-, 8-, and 16-ma class outputs symbol parameter min max unit conditions vcc 5v power supply voltage 4.5 5.5 v operation of interface in 5-v range vcc 3v power supply voltage 3.0 3.6 v operation of interface in 3.3-v range v ihc input high voltage 0.7 v dd v core_vdd = 3.0/4.5 v v ilc input low voltage 0.2 v dd v core_vdd = 3.6/5.5 v v oh output high voltage 2.4 v at rated i oh , interface v cc = 3.0 v i ohc output high voltage cmos interface vcc - 0.5 v at rated i ol i oh output current high, 2-ma-type driver - 2ma interface v cc = 3.0 v, v oh = 2.4 v +5 v = 4.5 v output current high, 4-ma-type driver - 3ma output current high, 8-ma-type driver - 4ma output current high, 16-ma-type driver - 5ma
advance data book v0.3 june 1998 184 electrical specifications cl-pd6833 pci-to-cardbus host adapter i ol output current low, 2-ma-type driver 2ma isa_v cc = 3.0 v, v ol = 0.5 v +5 v = 4.5 v output current low, 4-ma-type driver 4ma output current low, 8-ma-type driver 8ma output current low, 16-ma-type driver 16 ma table 15-5. operating current speci?cations (3.3 v) symbol parameter min typ max unit conditions icc tot(1) power supply current, operating tbd tbd tbd ma core_vdd = 3.3 v; +5v, socket_vcc, and pci_vcc = 5.0 v; p diss = < 85 mw icc tot(2) power supply current, suspend mode ( misc control 2 , bit 2 = 1) tbd m a core_vdd = 3.3 v; +5v, socket_vcc, and pci_vcc = 5.0 v; p diss = < 2 mw icc tot(3) power supply current, rst# active, no clocks tbd m a core_vdd = 3.3 v; +5v, socket_vcc, and pci_vcc = 5.0 v; p diss = < 1 mw table 15-4. general i/o pin dc speci?cations for 2-, 4-, 8-, and 16-ma class outputs (cont.) symbol parameter min max unit conditions
june 1998 185 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15.3 ac timing speci?cations this section includes system timing requirements for the cl-pd6833. unless otherwise speci?ed, timings are provided in nanoseconds (ns), at ttl input levels, with the ambient temperature varying from 0 c to 70 c, and v cc varying from 3.0 v to 3.6 v, or 4.5 v to 5.5 v dc. the pci bus speed is 33 mhz, unless otherwise speci?ed. note the following conventions: l a pound sign (#) at the end of a pin name indicates an active-low signal for the pci bus. l a dash (-) at the beginning of a pin name indicates an active-low signal for the pc card (pcmcia) bus. l an asterisk (*) at the end of a pin name indicates an active-low signal that is a general interface for the cl-pd6833. additionally, the following statements are true for all timing information: l all timings assume a load of 50 pf. l ttl signals are measured at ttl threshold; cmos signals are measured at cmos threshold. table 15-6. index of ac timing speci?cations title page number table 15-7. frame#, ad[31:0], c/be[3:0]#, and devsel# 186 table 15-8. trdy# and stop# delay 188 table 15-9. idsel timing in a con?guration cycle 189 table 15-10. par timing (pci bus) 190 table 15-11. pulse mode interrupt timing 191 table 15-12. memory read/write timing 193 table 15-13. word i/o read/write timing 194 table 15-14. pc card (pcmcia) read/write timing when system is 8-bit 196 table 15-15. normal byte read/write timing 197 table 15-16. 16-bit system to 8-bit i/o card (odd byte timing) 198
advance data book v0.3 june 1998 186 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15.3.1 pci bus timing table 15-7. frame#, ad[31:0], c/be[3:0]#, and devsel# symbol parameter pci_vcc = 3.3 v pci_vcc = 5.0 v units min max min max t 1 frame# setup to pci_clk 7C7C ns t 2 ad[31:0] (address) setup to pci_clk 7C7C ns t 3 ad[31:0] (address) hold from pci_clk 0C0C ns t 4 ad[31:0] (data) setup to pci_clk 7C7C ns t 5 ad[31:0] (data) active to high-z from pci_clk 0 28 0 28 ns t 6 c/be[3:0]# (bus command) setup to pci_clk 7C7C ns t 7 c/be[3:0]# (bus command) hold from pci_clk 0C0C ns t 8 c/be[3:0]# (byte enable) setup to pci_clk 7C7C ns t 9 devsel# delay from pci_clk C 11 C 11 ns t 10 devsel# high before high-z 1C1Cpci_clk
june 1998 187 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-1. frame#, ad[31:0], c/be[3:0]#, and devsel# (pci ? bus) pci_clk t 1 high-z high-z high-z high-z t 6 t 7 t 9 t 10 frame# ad[31:0] c/be[3:0]# devsel# trdy# address data bus byte enable high-z = high-impedance t 8 command high-z high-z stop# t 2 t 3 t 4 t 5 ad[31:0] address data write cycle read cycle t 9 12 3 4 high-z high-z
advance data book v0.3 june 1998 188 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-2. trdy# and stop# delay (pci ? bus) table 15-8. trdy# and stop# delay symbol parameter pci_vcc = 3.3 v pci_vcc = 5.0 v units min max min max t 1 trdy# active delay from pci_clk C 11 C 11 ns t 2 trdy# inactive delay from pci_clk C 11 C 11 ns t 3 trdy# high before high-z 1C1Cpci_clk t 4 stop# active delay from pci_clk C 11 C 11 ns t 5 stop# inactive delay from pci_clk C 11 C 11 ns t 6 stop# high before high-z 1C1Cpci_clk pci_clk t 1 t 2 t 3 trdy# high-z high-z high-z = high-impedance high-z t 4 high-z t 5 t 6 stop# frame#
june 1998 189 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-3. idsel timing in a con?guration cycle (pci ? bus) table 15-9. idsel timing in a con?guration cycle symbol parameter min max units t 1 idsel setup to pci_clk 7 C ns t 2 idsel hold from pci_clk 0 C ns high-z = high-impedance t 1 pci_clk t 2 con?g. address data byte enable idsel frame# ad[7:0] c/be[3:0]# id select con?g. read high-z high-z
advance data book v0.3 june 1998 190 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-4. par timing (pci bus) table 15-10. par timing (pci bus) symbol parameter min max units t 1 par setup to pci_clk (input to the cl-pd6833) 7 C ns t 2 par hold from pci_clk (input to the cl-pd6833) 0 C ns t 3 par valid delay from pci_clk (output from the cl-pd6833) C 11 ns t 4 par hold from pci_clk (output from the cl-pd6833) 0 C ns high-z = high-impedance t 2 pci_clk t 1 data bus byte enables c/be[3:0]# ad[31:0] address frame# pa r t 4 t 3 & command parity? data and byte enable parity? address command ? par goes high or low depending on ad[31:0] and c/be[3:0]# values. high-z high-z high-z
june 1998 191 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15.3.2 system interrupt timing figure 15-5. pulse mode interrupt timing table 15-11. pulse mode interrupt timing symbol parameter min max units t 1 irq[xx] low or high 15 18 pci_clk irq[xx] high-z high-z t 1 t 1 high-z = high-impedance
advance data book v0.3 june 1998 192 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15.3.3 pc card (pcmcia) bus timing calculations calculations for minimum pc card (pcmcia) cycles setup, command, and recovery timings are made by ?rst calculating factors derived from the applicable timer sets timing registers and then by applying the factor to an equation relating it to the internal clock period. the pc card cycle timing factors, in terms of the number of internal clocks, are calculated as follows: s = n val + 1 equation 15-1 c = n val + 1 equation 15-2 r = n val + 1 equation 15-3 n val is the speci?c selected multiplier value from the timer sets setup, command, and recovery timing registers (see chapter 12 for the description of these registers). from this, a pc card cycles setup, command, and recovery time for the selected timer set are calculated as follows: minimum setup time = (s tcp) - 10 ns equation 15-4 minimum command time = (c tcp) - 10 ns equation 15-5 minimum recovery time = (r + 1) tcp - 10 ns equation 15-6 tcp is the period of the internal clock. if pci_clk is selected ( misc control 2 register bit 0 is a 0) and operates at 33 mhz, and the clock input is not being divided ( misc control 2 register bit 4 is a 0), then: tcp = 30 ns equation 15-7 the timing diagrams that follow were derived for a cl-pd6833 using the pci clock at 33 mhz. the examples for the default values of the timing registers for timer set 0 are as follows: thus the minimum times for the default values are as follows: minimum setup time = (s tcp) - 10 ns = {[0 + 1] 30 ns} - 10 ns = 20 ns equation 15-8 minimum command time = (c tcp) - 10 ns = {[7 + 1] 30 ns} - 10 ns = 230 ns equation 15-9 minimum recovery time = (r + 1) tcp - 10 ns = {[5 + 1] 30 ns} - 10 ns = 170 ns equation 15-10 timing register name (timer set 0) i/o index value (default) resultant n val setup timing 0 3ah 00h 0 command timing 0 3bh 07h 7 recovery timing 0 3ch 04h 4
june 1998 193 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter 15.3.4 pc card (pcmcia) bus timing figure 15-6. memory read/write timing table 15-12. memory read/write timing symbol parameter min max units t 1 -reg, -ce[2:1], address, and write data setup to command active 1 (s tcp) - 10 ns t 2 command pulse width 2 (c tcp) - 10 ns t 3 address hold and write data valid from command inactive 3 (r tcp) - 10 ns t 4 -wait active from command active (c - 2) tcp - 10 ns t 5 command hold from -wait inactive 2 tcp ns t 6 data setup before -oe inactive (2 tcp) + 10 ns t 7 data hold after -oe inactive 0 ns t 8 data valid from -wait inactive tcp + 10 ns 1 the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 00h, the setup time would be 20 ns. s = n val + 1, see page 192 . 2 the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 07h, the command time would be 230 ns. c = n val + 1, see page 192 . 3 the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 04h, the hold (recovery) time would be 170 ns. r = n val + 1, see page 192 . -reg, -ce[2:1], t 1 t 2 t 4 t 3 -wait t 6 d[15:0] d[15:0] t 7 t 5 a[25:0] -oe, -we t 8 write cycle read cycle
advance data book v0.3 june 1998 194 electrical specifications cl-pd6833 pci-to-cardbus host adapter table 15-13. word i/o read/write timing symbol parameter min max units t 1 -reg or address setup to command active 1 (s tcp) C 10 ns t 2 command pulse width 2 (c tcp) C 10 ns t 3 address hold and write data valid from command inactive 3 (r tcp) C 10 ns t 4 -wait active from command active 4 (c C 2)tcp C 10 ns t 5 command hold from -wait inactive (2 tcp) + 10 ns t ref card -iois16 delay from valid address (pc card speci?cation) 35 ns t 6 -iois16 setup time before command end (3 tcp) + 10 ns t 7 -ce2 delay from -iois16 active 5 tcp C 10 ns t 8 data valid from -wait inactive tcp + 10 ns t 9 data setup before -iord inactive (2 tcp) + 10 ns t 10 data hold after -iord inactive 0 ns 1 the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 00h, the setup time would be 20 ns. s = n val + 1, see page 192 . 2 the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 07h, the command time would be 230 ns. c = n val + 1, see page 192 . 3 the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 04h, the hold (recovery) time would be 170 ns. r = n val + 1, see page 192 . 4 for command active timing programmed at 230 ns, maximum - wait timing is 100 ns after command active. 5 -iois16 must go low within 3tcp + 10 ns of the cycle beginning or -iois16 is ignored and -ce is not activated.
june 1998 195 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-7. word i/o read/write timing -iowr, -iord t 1 t 2 t 6 t 3 -iois16 t 7 -ce1 -reg, a[25:0] -ce2 d[15:0] t ref write cycle t 4 -wait t 5 t 9 d[15:0] t 10 t 8 read cycle
advance data book v0.3 june 1998 196 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-8. pc card (pcmcia) read/write timing (8-bit system) table 15-14. pc card (pcmcia) read/write timing when system is 8-bit symbol parameter min max units t 1 -reg or address setup to command active 1 (s tcp) C 10 ns t 2 command pulse width 2 (c tcp) C 10 ns t 3 address hold from command inactive 3 (r tcp) C 10 ns t 4 data setup before command inactive (2 tcp) + 10 ns t 5 data hold after command inactive 0 ns 1 the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 00h, the setup time would be 20 ns. s = n val + 1, see page 192 . 2 the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 07h, the command time would be 230 ns. c = n val + 1, see page 192 . 3 the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 04h, the hold (recovery) time would be 170 ns. r = n val + 1, see page 192 . -iowr, -iord, t 1 t 2 t 3 -ce1 -reg, a[25:0] d[7:0] odd/even data d[15:8] xx -oe, -we d[7:0] read cycle t 5 t 4 write cycle read or write cycle odd/even data
june 1998 197 advance data book v0.3 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-9. normal byte read/write timing table 15-15. normal byte read/write timing symbol parameter min max units t 1 address setup to command active 1 (s tcp) C 10 ns t 2 command pulse width 2 (c tcp) C 10 ns t 3 address hold from command inactive 3 (r tcp) C 10 ns 1 the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 00h, the setup time would be 20 ns. s = n val + 1, see page 192 . 2 the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 07h, the command time would be 230 ns. c = n val + 1, see page 192 . 3 the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 04h, the hold (recovery) time would be 170 ns. r = n val + 1, see page 192 . -reg, -iowr, -iord, t 1 t 2 t 3 -ce1 a[25:0] -ce2 d[7:0] odd/even data d[15:8] xx -oe, -we write cycle read or write cycle d[7:0] read cycle odd/even data note: this is the normal byte read/write timing for all other byte accesses, including odd i/o cycles where -iois16 is low.
advance data book v0.3 june 1998 198 electrical specifications cl-pd6833 pci-to-cardbus host adapter figure 15-10. 16-bit system to 8-bit i/o card (odd byte timing) table 15-16. 16-bit system to 8-bit i/o card (odd byte timing) symbol parameter min max units t 1 address change to -iois16 inactive 4 (3tcp) + 10 ns t 2 -iois16 inactive to -ce2 inactive 20 ns t 3 -iois16 inactive to -ce1 active 20 ns t 4 address setup to command active 1 (s tcp) C 10 ns t 5 command pulse width 2 (c tcp) C 10 ns t 6 address hold from command inactive 3 (r tcp) C 10 ns 1 the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 00h, the setup time would be 20 ns. s = n val + 1, see page 192 . 2 the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 07h, the command time would be 230 ns. c = n val + 1, see page 192 . 3 the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 04h, the hold (recovery) time would be 170 ns. r = n val + 1, see page 192 . 4 -iois16 level from card must be valid within 3 clocks of an address change to the card. -reg, -iois16 t 3 -ce1 a[25:0] -ce2 d[7:0] odd data t 2 write cycle d[7:0] read cycle odd data d[15:8] xx read or write cycle -iowr, -iord t 4 t 5 t 6 t 1
june 1998 199 advance data book v0.3 package specifications cl-pd6833 pci-to-cardbus host adapter 16. package specifications notes: 1) dimensions are in millimeters (inches), and the controlling dimension is millimeter. 2) drawing above does not re?ect exact package pin count. 3) before beginning any new design with this device, please contact cirrus logic for the latest package information. pin 1 indicator 25.50 (1.004) ref 30.35 (1.195) 30.85 (1.215) 0.13 (0.005) 0.28 (0.011) 27.90 (1.098) 28.10 (1.106) 25.50 (1.004) ref 0.50 (0.0197) bsc 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 3.17 (0.125) 3.67 (0.144) 0 min 7 max 0.09 (0.004) 0.23 (0.009) 4.07 (0.160) max 0.40 (0.016) 0.75 (0.030) 0.25 (0.010) min 1.30 (0.051) ref pin 1 pin 208 208-pin mqfp cl-pd6833
advance data book v0.3 june 1998 200 package specifications cl-pd6833 pci-to-cardbus host adapter notes: 1) dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) drawing above does not re?ect exact package pin count. 3) before beginning any new design with this device, please contact cirrus logic for the latest package information. pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) bsc pin 1 pin 208 1.60 (0.063) 0.15 (0.006) cl-pd6833 208-pin lqfp
june 1998 201 advance data book v0.3 ordering information cl-pd6833 pci-to-cardbus host adapter 17. ordering information the order number for the part is: cl C pd6833 C qc C a cirrus logic, inc. product line: part number package type: temperature range: revision ? c = commercial q = metric quad flat pack ? contact cirrus logic for up-to-date information on revisions. portable products v = low-pro?le quad flat pack
advance data book v0.3 june 1998 202 ordering information cl-pd6833 pci-to-cardbus host adapter notes
june 1998 203 advance data book v0.3 pin listings cl-pd6833 pci-to-cardbus host adapter appendix a a. pin listings this appendix contains the following pin listings: table / figure number table / figure title page table a-1 cl-pd6833 pin listing in numerical order using pc card 16 (r2) signal names 204 table a-2 cl-pd6833 pin listing in numerical order using pc card 32 (cardbus) signal names 205 table a-3 cl-pd6833 pin listing in alphabetical order using pc card 16 (r2) signal names 206 table a-4 cl-pd6833 pin listing in numerical order using pc card 32 (cardbus) signal names 207 figure a-1 pc card socket signal names (for reference only) 208 table a-5 pci bus pin listing (for reference only) 209
advance data book v0.3 june 1998 204 pin listings cl-pd6833 pci-to-cardbus host adapter table a-1. cl-pd6833 pin listing in numerical order using pc card 16 (r2) signal names no. pin name 1 pci_clk 2 gnt# 3 req# 4ad31 5ad30 6 pci_vcc 7ad29 8ad28 9ad27 10 ad26 11 ad25 12 ad24 13 c/be3# 14 ring_gnd 15 idsel 16 ad23 17 ad22 18 ad21 19 ad20 20 ad19 21 pci_vcc 22 ad18 23 ad17 24 ad16 25 c/be2# 26 core_gnd 27 frame# 28 ring_gnd 29 irdy# 30 trdy# 31 devsel# 32 stop# 33 perr# 34 serr# 35 par 36 c/be1# 37 pci_vcc 38 ad15 39 ad14 40 ad13 41 ad12 42 ad11 43 ad10 44 ring_gnd 45 ad9 46 ad8 47 c/be0# 48 ad7 49 ad6 50 pci_vcc 51 ad5 52 ad4 53 ad3 54 ad2 55 ad1 56 ad0 57 ring_gnd 58 lock# 59 a_d3 60 a_socket_vcc 61 a_-cd1 62 a_d4 63 a_d11 64 a_d5 65 a_d12 66 a_d6 67 a_d13 68 a_d7 69 a_d14 70 a_-ce1 71 a_d15 72 ring_gnd 73 a_a10 74 a_-ce2 75 a_-oe 76 a_vs1 77 a_a11 78 a_-iord 79 core_vdd 80 a_a9 81 a_-iowr 82 a_a8 83 a_a17 84 a_a13 85 a_a18 86 a_a14 87 core_gnd 88 a_a19 89 a_-we 90 a_a20 91 a_rdy/-ireq 92 a_a21 93 a_a16 94 a_a22 95 a_a15 96 a_a23 97 a_a12 98 a_socket_vcc 99 a_a24 100 a_a7 101 ring_gnd 102 a_a25 103 a_a6 104 a_vs2 105 a_a5 106 a_reset no. pin name 107 a_a4 108 a_-wait 109 a_a3 110 a_-inpack 111 a_a2 112 a_-reg 113 a_a1 114 a_bvd2/-spkr/-led 115 ring_gnd 116 a_a0 117 a_socket_vcc 118 a_bvd1/-stschg/-ri 119 a_d0 120 a_d8 121 a_d1 122 a_d9 123 a_d2 124 a_d10 125 a_wp/-iois16 126 a_-cd2 127 +5v 128 spkr_out*/gpio3 129 ring_gnd 130 slatch/smbclk 131 sdata/smbdata 132 sclk 133 led_out*/ hw_suspend#/ pme#/gpio4 134 core_vdd 135 b_d3 136 b_-cd1 137 b_d4 138 b_d11 139 b_d5 140 b_d12 141 b_d6 142 b_d13 143 b_socket_vcc 144 b_d7 145 b_d14 146 ring_gnd 147 b_-ce1 148 b_d15 149 b_a10 150 b_-ce2 151 b_-oe 152 b_vs1 153 b_a11 154 b_-iord 155 b_a9 156 b_-iowr 157 b_a8 no. pin name 158 b_a17 159 b_a13 160 b_socket_vcc 161 b_a18 162 b_a14 163 ring_gnd 164 b_a19 165 b_-we 166 b_a20 167 b_rdy/-ireq 168 b_a21 169 b_a16 170 b_a22 171 b_a15 172 b_a23 173 b_a12 174 b_a24 175 b_a7 176 b_a25 177 core_gnd 178 b_a6 179 b_vs2 180 core_vdd 181 b_a5 182 b_reset 183 b_a4 184 b_-wait 185 b_a3 186 b_-inpack 187 b_a2 188 b_-reg# 189 b_a1 190 b_bvd2/-spkr/-led 191 b_a0 192 b_bvd1/-stschg/-ri 193 ring_gnd 194 b_d0 195 b_d8 196 b_d1 197 b_d9 198 b_d2 199 b_d10 200 b_socket_vcc 201 b_wp/-iois16 202 b_-cd2 203 inta#/led1*/gpio1 204 intb#/ri_out*/pme# 205 sout#/isld/irqser 206 sin#/isdat/ led2*/gpio2 207 rst# 208 clkrun# no. pin name
june 1998 205 advance data book v0.3 pin listings cl-pd6833 pci-to-cardbus host adapter table a-2. cl-pd6833 pin listing in numerical order using pc card 32 (cardbus) signal names no. pin name 1 pci_clk 2 gnt# 3 req# 4ad31 5ad30 6 pci_vcc 7ad29 8ad28 9ad27 10 ad26 11 ad25 12 ad24 13 c/be3# 14 ring_gnd 15 idsel 16 ad23 17 ad22 18 ad21 19 ad20 20 ad19 21 pci_vcc 22 ad18 23 ad17 24 ad16 25 c/be2# 26 core_gnd 27 frame# 28 ring_gnd 29 irdy# 30 trdy# 31 devsel# 32 stop# 33 perr# 34 serr# 35 par 36 c/be1# 37 pci_vcc 38 ad15 39 ad14 40 ad13 41 ad12 42 ad11 43 ad10 44 ring_gnd 45 ad9 46 ad8 47 c/be0# 48 ad7 49 ad6 50 pci_vcc 51 ad5 52 ad4 53 ad3 54 ad2 55 ad1 56 ad0 57 ring_gnd 58 lock# 59 a_cad0 60 a_socket_vcc 61 a_ccd1# 62 a_cad1 63 a_cad2 64 a_cad3 65 a_cad4 66 a_cad5 67 a_cad6 68 a_cad7 69 a_rfu 70 a_ccbe0# 71 a_cad8 72 ring_gnd 73 a_cad9 74 a_cad10 75 a_cad11 76 a_cvs1 77 a_cad12 78 a_cad13 79 core_vdd 80 a_cad14 81 a_cad15 82 a_ccbe1# 83 a_cad16 84 a_cpar 85 a_rfu 86 a_cperr# 87 core_gnd 88 a_cblock# 89 a_cgnt# 90 a_cstop# 91 a_cint# 92 a_cdevsel# 93 a_cclk 94 a_ctrdy# 95 a_cirdy# 96 a_cframe# 97 a_ccbe2# 98 a_socket_vcc 99 a_cad17 100 a_cad18 101 ring_gnd 102 a_cad19 103 a_cad20 104 a_cvs2 105 a_cad21 106 a_crst# no. pin name 107 a_cad22 108 a_cserr# 109 a_cad23 110 a_creq# 111 a_cad24 112 a_ccbe3# 113 a_cad25 114 a_caudio 115 ring_gnd 116 a_cad26 117 a_socket_vcc 118 a_cstschg 119 a_cad27 120 a_cad28 121 a_cad29 122 a_cad30 123 a_d2 124 a_cad31 125 a_cclkrun# 126 a_ccd2# 127 +5v 128 spkr_out*/gpio3 129 ring_gnd 130 slatch /smbclk 131 sdata /smbdata 132 sclk 133 led_out*/ hw_suspend#/ pme#/gpio4 134 core_vdd 135 b_cad0 136 b_ccd1# 137 b_cad1 138 b_cad2 139 b_cad3 140 b_cad4 141 b_cad5 142 b_cad6 143 b_socket_vcc 144 b_cad7 145 b_rfu 146 ring_gnd 147 b_ccbe0# 148 b_cad8 149 b_cad9 150 b_cad10 151 b_cad11 152 b_cvs1 153 b_cad12 154 b_cad13 155 b_cad14 156 b_cad15 157 b_ccbe1# 158 b_cad16 no. pin name 159 b_cpar 160 b_socket_vcc 161 b_rfu 162 b_cperr# 163 ring_gnd 164 b_cblock# 165 b_cgnt# 166 b_cstop# 167 b_cint# 168 b_cdevsel# 169 b_cclk 170 b_ctrdy# 171 b_cirdy# 172 b_cframe# 173 b_ccbe2# 174 b_cad17 175 b_cad18 176 b_cad19 177 core_gnd 178 b_cad20 179 b_cvs2 180 core_vdd 181 b_cad21 182 b_crst# 183 b_cad22 184 b_cserr# 185 b_cad23 186 b_creq# 187 b_cad24 188 b_ccbe3# 189 b_cad25 190 b_caudio 191 b_cad26 192 b_cstschg 193 ring_gnd 194 b_cad27 195 b_cad28 196 b_cad29 197 b_cad30 198 b_rfu 199 b_cad31 200 b_socket_vcc 201 b_cclkrun# 202 b_ccd2# 203 inta#/led1*/gpio1 204 intb#/ri_out*/pme# 205 sout#/isld/irqser 206 sin#/isdat/ led2*/gpio2 207 rst# 208 clkrun# no. pin name
advance data book v0.3 june 1998 206 pin listings cl-pd6833 pci-to-cardbus host adapter table a-3. cl-pd6833 pin listing in alphabetical order using pc card 16 (r2) signal names pin name no. a_a0 116 a_a1 113 a_a2 111 a_a3 109 a_a4 107 a_a5 105 a_a6 103 a_a7 100 a_a8 82 a_a9 80 a_a10 73 a_a11 77 a_a12 97 a_a13 84 a_a14 86 a_a15 95 a_a16 93 a_a17 83 a_a18 85 a_a19 88 a_a20 90 a_a21 92 a_a22 94 a_a23 96 a_a24 99 a_a25 102 a_bvd1/-stschg/-ri 118 a_bvd2/-spkr/-led 114 a_-cd1 61 a_-cd2 126 a_-ce1 70 a_-ce2 74 a_d0 119 a_d1 121 a_d2 123 a_d3 59 a_d4 62 a_d5 64 a_d6 66 a_d7 68 a_d8 120 a_d9 122 a_d10 124 a_d11 63 a_d12 65 a_d13 67 a_d14 69 a_d15 71 a_-inpack 110 a_-iord 78 a_-iowr 81 a_-oe 75 a_rdy/-ireq 91 a_-reg 112 a_reset 106 a_vs1 76 a_vs2 104 a_-wait 108 a_-we 89 a_wp/-iois16 125 a_socket_vcc 60 a_socket_vcc 98 a_socket_vcc 117 ad0 56 ad1 55 ad2 54 ad3 53 ad4 52 ad5 51 ad6 49 ad7 48 ad8 46 ad9 45 ad10 43 ad11 42 ad12 41 ad13 40 ad14 39 ad15 38 ad16 24 ad17 23 ad18 22 ad19 20 ad20 19 ad21 18 ad22 17 ad23 16 ad24 12 ad25 11 ad26 10 ad27 9 ad28 8 ad29 7 ad30 5 ad31 4 b_a0 191 b_a1 189 b_a2 187 b_a3 185 b_a4 183 b_a5 181 b_a6 178 b_a7 175 b_a8 157 b_a9 155 b_a10 149 pin name no. b_a11 153 b_a12 173 b_a13 159 b_a14 162 b_a15 171 b_a16 169 b_a17 158 b_a18 161 b_a19 164 b_a20 166 b_a21 168 b_a22 170 b_a23 172 b_a24 174 b_a25 176 b_bvd1/-stschg/-ri 192 b_bvd2/-spkr/-led 190 b_-cd1 136 b_-cd2 202 b_-ce1 147 b_-ce2 150 b_d0 194 b_d1 196 b_d2 198 b_d3 135 b_d4 137 b_d5 139 b_d6 141 b_d7 144 b_d8 195 b_d9 197 b_d10 199 b_d11 138 b_d12 140 b_d13 142 b_d14 145 b_d15 148 b_-inpack 186 b_-iord 154 b_-iowr 156 b_-oe 151 b_rdy/-ireq 167 b_-reg# 188 b_reset 182 b_vs1 152 b_vs2 179 b_-wait 184 b_-we 165 b_wp/-iois16 201 b_socket_vcc 143 b_socket_vcc 160 b_socket_vcc 200 c/be0# 47 pin name no. c/be1# 36 c/be2# 25 c/be3# 13 clkrun# 208 core_gnd 26 core_gnd 87 core_gnd 177 core_vdd 79 core_vdd 134 core_vdd 180 devsel# 31 frame# 27 gnt# 2 idsel 15 irdy# 29 inta#/led1*/gpio1 203 intb#/ri_out*/ pme# 204 led_out*/ hw_suspend#/ pme#/gpio4 133 lock# 58 pa r 3 5 pci_clk 1 pci_vcc 6 pci_vcc 21 pci_vcc 37 pci_vcc 50 perr# 33 req# 3 ring_gnd 14 ring_gnd 28 ring_gnd 44 ring_gnd 57 ring_gnd 72 ring_gnd 101 ring_gnd 115 ring_gnd 129 ring_gnd 146 ring_gnd 163 ring_gnd 193 rst# 207 sclk 132 sdata/smbdata 131 serr# 34 sin#/isdat/ led2*/gpio2 206 slatch/smbclk 130 sout#/isld/irqser 205 spkr_out*/gpio3 128 stop# 32 trdy# 30 +5v 127 pin name no.
june 1998 207 advance data book v0.3 pin listings cl-pd6833 pci-to-cardbus host adapter table a-4. cl-pd6833 pin listing in alphabetical order using pc card 32 (cardbus) signal names pin name no. a_cad0 59 a_cad1 62 a_cad2 63 a_cad3 64 a_cad4 65 a_cad5 66 a_cad6 67 a_cad7 68 a_cad8 71 a_cad9 73 a_cad10 74 a_cad11 75 a_cad12 77 a_cad13 78 a_cad14 80 a_cad15 81 a_cad16 83 a_cad17 99 a_cad18 100 a_cad19 102 a_cad20 103 a_cad21 105 a_cad22 107 a_cad23 109 a_cad24 111 a_cad25 113 a_cad26 116 a_cad27 119 a_cad28 120 a_cad29 121 a_cad30 122 a_cad31 124 a_caudio 114 a_cblock# 88 a_ccbe0# 70 a_ccbe1# 82 a_ccbe2# 97 a_ccbe3# 112 a_ccd1# 61 a_ccd2# 126 a_cclk 93 a_cclkrun# 125 a_cdevsel# 92 a_cframe# 96 a_cgnt# 89 a_cint# 91 a_cirdy# 95 a_cpar 84 a_cperr# 86 a_creq# 110 a_crst# 106 a_cserr# 108 a_cstop# 90 a_cstschg 118 a_ctrdy# 94 a_cvs1 76 a_cvs2 104 a_d2 123 a_rfu 69 a_rfu 85 a_socket_vcc 60 a_socket_vcc 98 a_socket_vcc 117 ad0 56 ad1 55 ad2 54 ad3 53 ad4 52 ad5 51 ad6 49 ad7 48 ad8 46 ad9 45 ad10 43 ad11 42 ad12 41 ad13 40 ad14 39 ad15 38 ad16 24 ad17 23 ad18 22 ad19 20 ad20 19 ad21 18 ad22 17 ad23 16 ad24 12 ad25 11 ad26 10 ad27 9 ad28 8 ad29 7 ad30 5 ad31 4 b_cad0 135 b_cad1 137 b_cad2 138 b_cad3 139 b_cad4 140 b_cad5 141 b_cad6 142 b_cad7 144 b_cad8 148 b_cad9 149 b_cad10 150 pin name no. b_cad11 151 b_cad12 153 b_cad13 154 b_cad14 155 b_cad15 156 b_cad16 158 b_cad17 174 b_cad18 175 b_cad19 176 b_cad20 178 b_cad21 181 b_cad22 183 b_cad23 185 b_cad24 187 b_cad25 189 b_cad26 191 b_cad27 194 b_cad28 195 b_cad29 196 b_cad30 197 b_cad31 199 b_caudio 190 b_cblock# 164 b_ccbe0# 147 b_ccbe1# 157 b_ccbe2# 173 b_ccbe3# 188 b_ccd1# 136 b_ccd2# 202 b_cclk 169 b_cclkrun# 201 b_cdevsel# 168 b_cframe# 172 b_cgnt# 165 b_cint# 167 b_cirdy# 171 b_cpar 159 b_cperr# 162 b_creq# 186 b_crst# 182 b_cserr# 184 b_stop# 166 b_cstschg 192 b_socket_vcc 143 b_socket_vcc 160 b_socket_vcc 200 b_ctrdy# 170 b_cvs1 152 b_cvs2 179 b_rfu 145 b_rfu 161 b_rfu 198 c/be0# 47 pin name no. c/be1# 36 c/be2# 25 c/be3# 13 clkrun# 208 core_gnd 26 core_gnd 87 core_gnd 177 core_vdd 79 core_vdd 134 core_vdd 180 devsel# 31 frame# 27 gnt# 2 idsel 15 irdy# 29 inta#/led1*/gpio1 203 intb#/ri_out*/ pme# 204 led_out*/ hw_suspend#/ pme#/gpio4 133 lock# 58 pa r 3 5 pci_clk 1 pci_vcc 6 pci_vcc 21 pci_vcc 37 pci_vcc 50 perr# 33 req# 3 ring_gnd 14 ring_gnd 28 ring_gnd 44 ring_gnd 57 ring_gnd 72 ring_gnd 101 ring_gnd 115 ring_gnd 129 ring_gnd 146 ring_gnd 163 ring_gnd 193 rst# 207 sclk 132 sdata/smbdata 131 serr# 34 sin#/isdat/ led2*/gpio2 206 slatch/smbclk 130 sout#/isld/ irqser 205 spkr_out*/gpio3 128 stop# 32 trdy# 30 +5v 127 pin name no.
advance data book v0.3 june 1998 208 pin listings cl-pd6833 pci-to-cardbus host adapter figure a-1. pc card socket signal names (for reference only) cad6 cad10 cad13 cvs1 cad16 rfu cad8 cad2 cad4 cad15 4 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gnd v cc ccd1# cblock# 38 35 36 37 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 rfu cstop# cdevsel# v pp 2 ctrdy# cframe# cad17 25 26 27 28 29 30 31 32 33 34 59 60 61 62 63 64 65 66 67 68 cad19 cvs2 crst# cserr# creq# cc/be3# cad30 cad31 ccd2# gnd caudio cstschg cad28 cad5 cad9 cad12 cad11 cc/be1# cad7 cc/be0# cad1 cad3 cad14 gnd v cc cad0 cperr# cpar cgnt# cint# v pp 1 cclk cirdy# cc/be2# cad18 cad20 cad21 cad22 cad23 cad24 cad29 rfu cclkrun# gnd cad25 cad26 cad27 data 13 ce2# reserved vs1#/refresh address 17 data 14 data 15 data 11 data 12 reserved ground v cc cd1# address 19 address 18 address 20 address 21 v pp 2 address 22 address 23 address 24 address 25 vs2#/reserved reset wait# reserved reg# data 9 data 10 cd2# ground bvd2 bvd1 data 8 data 6 address 10 address 11 oe# address 8 data 7 ce1# data 4 data 5 address 9 ground v cc data 3 address 14 address 13 we# ready v pp 1 address 16 address 15 address 12 address 7 address 6 address 5 address 4 address 3 address 2 data 1 data 2 wp ground address 1 address 0 data 0 pc card 16 pc card 32 pc card 16 pc card 32 note: rfu is reserved for future use. vs1# was named refresh in pcmcia 2.1. (r2) (cardbus) (cardbus) (r2)
june 1998 209 advance data book v0.3 pin listings cl-pd6833 pci-to-cardbus host adapter table a-5. pci bus pin listing (for reference only) pin 5-v board universal board 3.3-v board side b side a side b side a side b side a 1 +12v trst# +12v trst# +12v trst# 2 tck +12v tck +12v tck +12v 3 ground tms ground tms ground tms 4 tdo tdi tdo tdi tdo tdi 5 +5v +5v +5v +5v +5v +5v 6 +5v inta# +5v inta# +5v inta# 7 intb# intc# intb# intc# intb# intc# 8 intd# +5v intd# +5v intd# +5v 9 prsnt1# reserved prsnt1# reserved prsnt1# reserved 10 reserved +5v reserved +v i/o reserved +3.3v 11 prsnt2# reserved prsnt2# reserved prsnt2# reserved 12 ground ground keyway keyway 13 ground ground keyway keyway 14 reserved reserved reserved reserved reserved reserved 15 ground rst# ground rst# ground rst# 16 clk +5v clk +v i/o clk +3.3v 17 ground gnt# ground gnt# ground gnt# 18 req# ground req# ground req# ground 19 +5v ground +v i/o ground +3.3v ground 20 ad[31] ad[30] ad[31] ad[30] ad[31] ad[30] 21 ad[29] +3.3v ad[29] +3.3v ad[29] +3.3v 22 ground ad[28] ground ad[28] ground ad[28] 23 ad[27] ad[26] ad[27] ad[26] ad[27] ad[26] 24 ad[25] ground ad[25] ground ad[25] ground 25 +3.3v ad[24] +3.3v ad[24] +3.3v ad[24] 26 c/be[3]# idsel c/be[3]# idsel c/be[3]# idsel 27 ad[23[ +3.3v ad[23[ +3.3v ad[23[ +3.3v 28 ground ad[22] ground ad[22] ground ad[22] 29 ad[21] ad[20] ad[21] ad[20] ad[21] ad[20] 30 ad[19] ground ad[19] ground ad[19] ground 31 +3.3v ad[18] +3.3v ad[18] +3.3v ad[18] 32 ad[17] ad[16] ad[17] ad[16] ad[17] ad[16] 33 c/be[2]# +3.3v c/be[2]# +3.3v c/be[2]# +3.3v
advance data book v0.3 june 1998 210 pin listings cl-pd6833 pci-to-cardbus host adapter 34 ground frame# ground frame# ground frame# 35 irdy# ground irdy# ground irdy# ground 36 +3.3v trdy# +3.3v trdy# +3.3v trdy# 37 devsel# ground devsel# ground devsel# ground 38 ground stop# ground stop# ground stop# 39 lock# +3.3v lock# +3.3v lock# +3.3v 40 perr# sdone perr# sdone perr# sdone 41 +3.3v sbo# +3.3v sbo# +3.3v sbo# 42 serr# ground serr# ground serr# ground 43 +3.3v par +3.3v par +3.3v par 44 c/be[1]# ad[15] c/be[1]# ad[15] c/be[1]# ad[15] 45 ad[14] +3.3v ad[14] +3.3v ad[14] +3.3v 46 ground ad[13] ground ad[13] ground ad[13] 47 ad[12] ad[11] ad[12] ad[11] ad[12] ad[11] 48 ad[10] ground ad[10] ground ad[10] ground 49 ground ad[09] m66en ad[09] m66en ad[09] 50 keyway keyway ground ground 51 keyway keyway ground ground 52 ad[08] c/be[0]# ad[08] c/be[0]# ad[08] c/be[0]# 53 ad[07] +3.3v ad[07] +3.3v ad[07] +3.3v 54 +3.3v ad[08] +3.3v ad[08] +3.3v ad[08] 55 ad[05] ad[04] ad[05] ad[04] ad[05] ad[04] 56 ad[03] ground ad[03] ground ad[03] ground 57 ground ad[02] ground ad[02] ground ad[02] 58 ad[01] ad[00] ad[01] ad[00] ad[01] ad[00] 59 +5v +5v +v i/o +v i/o +3.3v +3.3v 60 ack64# ack64# ack64# req64# ack64# req64# 61 +5v +5v +5v +5v +5v +5v 62 +5v +5v +5v +5v +5v +5v table a-5. pci bus pin listing (for reference only) (cont.) pin 5-v board universal board 3.3-v board side b side a side b side a side b side a
june 1998 211 advance v0.3 index cl-pd6833 pci-to-cardbus host adapter numerics 8-bit register example 42 structure 42 a abbreviations 7 absolute maximum ratings 181 ac speci?cations 185 C 198 acronyms 7 application notes, related con?guring pcmcia sockets for ata drive interface (an-pd5) 179 interrupt signalling modes for the cl-pd6730 and cl-pd6832 (an-pd8) 32 zoomed video port implementation (an-pd10) 29 ata disk interface 179 ata mode operation 37 , 179 pin cross-reference 179 attribute memory 25 b bit naming conventions 7 numbering conventions 7 bus sizing 37 c card detect 38 insertion 37 removal 36 voltage sense 38 cardbus cards. see pc card 32 (cardbus) cardbus registers control 82 event force 80 present state 78 status event 75 status mask 77 common memory 25 conventions abbreviations 7 acronyms 7 bit naming 7 , 45 bit numbering 7 internal registers 7 numbers and units 8 pin naming 12 register bit types 45 register headings 45 special function bits 45 d dc speci?cations general 181 general i/o pin for 2-, 4-, 8-, and 16-ma class outputs 183 operating current speci?cations (3.3 v) 184 pc card (pcmcia) bus interface 182 pci bus interface 183 device control registers card status change 98 chip revision 91 interface status 92 interrupt and general control 96 management interrupt con?guration 99 mapping enable 101 power control 94 device identi?cation and implementation scheme 159 dma pci/way 34 transfer size 70 dma operation registers dma command and status 175 high address 173 high count 174 low address 172 low count 174 mask 178 master clear 178 mid count 174 mid high address 173 mid low address 172 mode 177 request 176 e electrical speci?cations absolute maximum ratings 181 ac timing speci?cations 185C198 dc speci?cations. see dc speci?cations extension registers ata control 138 index
advance data book v0.3 june 1998 212 index cl-pd6833 pci-to-cardbus host adapter chip information 137 device identi?cation and implementation scheme device capability byte a 161 device capability byte b 162 device implementation byte a 163 device implementation byte b 164 device implementation byte c 165 device implementation byte d 166 mask revision byte 159 product id byte 160 extended data 141 extension control 1 142 gen map 0C6 upper address (memory) 143 gpio input control 147 gpio input data 148 gpio output control 147 gpio output data 148 pin multiplex control 0 144 pin multiplex control 1 146 extended index 140 fifo control 134 misc control 1 132 misc control 2 136 prefetch window 149 extension card status change 156 gen map 0C6 extra control (i/o) 154 gen map 0C6 extra control (memory) 155 misc control 3 151 misc control 4 157 misc control 5 158 misc control 6 158 pc card space control 150 pci space control 149 smb socket power control address 153 window type select 150 external-hardware serial signalling mode 36 g general interface pins 21C23 general mapping registers (for i/o mode). see general window mapping registers general mapping registers (for memory mode). see general window mapping registers general window mapping registers general mapping (for i/o mode) gen map 0C6 end address high (i/o) 122 gen map 0C6 end address low (i/o) 121 gen map 0C6 offset address high (i/o) 124 gen map 0C6 offset address low (i/o) 123 gen map 0C6 start address high (i/o) 120 gen map 0C6 start address low (i/o) 119 general mapping (for memory mode) gen map 0C6 end address high (memory) 128 gen map 0C6 end address low (memory) 127 gen map 0C6 offset address high (memory) 130 gen map 0C6 offset address low (memory) 129 gen map 0C6 start address high (memory) 126 gen map 0C6 start address low (memory) 125 ground pins 24 h hardware suspend mode 34 host access to registers 42 i i/o window mapping registers. see window mapping registers i/o window options 27 i/o-to-i/o window 28 i/o-to-memory window 29 ide. see ata disk interface index register 42 interrupt signalling 151 interrupt signalling mode external-hardware 32 overview 31 pc/pci serial 33 pci 33 pci/way 32 interrupts classes 31 management 31 overview 30 socket or card 31 m mask revision 159 memory map windows 110 memory window mapping register. see window mapping registers memory window options 26 memory-to-i/o window 28 memory-to-memory window 27 modes ata . see ata mode external-hardware serial signalling 36 hardware suspend 34 interrupt signalling. see interrupt signalling mode memory-mapped 44 request 177
june 1998 213 advance data book v0.3 index cl-pd6833 pci-to-cardbus host adapter system management bus signalling 36 texas instruments tps2202aidf serial signalling 35 transfer 177 o operation registers data 90 index 85 C 86 ordering information 201 p package speci?cations 199 pc card de?nition 25 enabling output signals to socket 94 pc card standard 25 sensing 37 socket signal names 208 timing 37 pc card (pcmcia) bus timing 16-bit system to 8-bit i/o card (odd byte timing) 198 memory read/write timing 193 normal byte read/write timing 197 pc card (pcmcia) read/write timing when system is 8-bit 196 word i/o read/write timing 194 C 195 pc card 16 (r2) attribute memory 25 common memory 25 description 25 i/o-type cards 25 memory-type cards 25 pin diagram 10 signal names 204 , 206 windowing capabilities 26 pc card 32 (cardbus) description 25 pin diagram 11 signal names 205 , 207 pci bus interface pins 13C15 pci bus pin listing 209 pci bus timing frame#, ad[31:0], c/be[3:0]#, and devsel# 186 C 187 idsel timing in a con?guration cycle 189 par timing (pci bus) 190 trdy# and stop# delay 188 pci con?guration registers cache line size, latency timer, header type, and bist 53 cardbus status 55 command and status 49 con?guration miscellaneous 1 73 dma slave con?guration 70 i/o base 0C1 60 i/o limit 0C1 61 interrupt line, interrupt pin, and bridge control 62 memory base 0C1 58 memory base address 54 memory limit 0C1 59 pc card 16-bit if legacy mode base address 66 pci bus number, cardbus number, subordinate bus number, and cardbus latency timer 57 power management 67 power management control and status 68 revision id and class code 52 socket number 71 subsystem vendor id and subsystem device id 65 vendor id and device id 48 pci/way dma 34 pcmcia 25 pin information a_pin name 15 ata pin cross-reference 179 b_pin name 15 conventions 12 general interface pins 21C23 ground pins 24 pc card socket signal names 208 pci bus interface pins 13C15 pin diagrams 10 C 11 pin listings 203C210 power control pins 21C23 power pins 24 socket interface pins 15C21 power control pins 21C23 power management 34 power pins 24 power-on setup 44 pulse mode interrupt timing 191 r r2 cards. see pc card 16 (r2) registers cardbus. see cardbus registers conventions 7 device control. see device control registers dma operation. see dma operation registers extended data 43 extended index 43 extension. see extension registers
advance data book v0.3 june 1998 214 index cl-pd6833 pci-to-cardbus host adapter general window mapping. see general window mapping registers host access to 42 index register 42 operation. see operation registers pci con?guration. see pci con?guration registers timing. see timing registers window mapping. see window mapping registers request mode 177 s socket interface pins 15C21 socket interface power state 68 socket number 71 socket power commands, enabling 94 control 35 control con?guration 35 management features 35 system architecture 25 system interrupt timing 191 system management bus signalling mode 36 t texas instruments tps2202aidf serial signalling mode 35 timing ac timing speci?cations 185C198 pc card 37 pc card (pcmcia) bus timing calculations 192 pc card (pcmcia) bus timing. see pc card (pcmcia) bus timing pci bus timing. see pci bus timing pulse mode timing 191 system interrupt timing 191 timing registers command timing 0C1 168 recovery timing 0C1 169 setup timing 0C1 167 transfer mode 177 u upgrading from the cl-pd6832 38 w window mapping registers i/o window mapping card i/o map 0C1 offset address high 109 card i/o map 0C1 offset address low 109 i/o window control 105 system i/o map 0C1 end address high 108 system i/o map 0C1 end address low 108 system i/o map 0C1 start address high 107 system i/o map 0C1 start address low 107 memory window mapping card memory map 0C4 offset address high 115 card memory map 0C4 offset address low 114 system memory map 0C4 end address high 113 system memory map 0C4 end address low 112 system memory map 0C4 start address high 111 system memory map 0C4 start address low 110 window option i/o 27 i/o-to-i/o window 28 i/o-to-memory window 29 memory 26 memory-to-i/o window 28 memory-to-memory 27 windowing capabilities 26 windows, memory mapping 110 z zv (zoomed video) port 29 zv port implementation, typical 30
june 1998 215 advance data book v0.3 index cl-pd6833 pci-to-cardbus host adapter notes
cirrus logic, inc. publications ordering: 800/359-6414 (usa) or 510/249-4200 3100 west warren ave., fremont, ca 94538 worldwide web: http://www.cirrus.com tel: 510/623-8300 fax: 510/252-6020 346833-003 cl-pd6833 advance data sheet v0.3 direct sales of?ces high-value systems in silicon cirrus logic is a premier supplier of advanced integrated circuits that combine mixed-signal processing, precision analog techniques, embedded processors, and application-speci?c algorithms into system-on-a-chip solutions for existing and emerging growth markets. enhanced by strong systems expertise in selected markets, the companys products add high value to major brands worldwide in magnetic and optical storage, networking communications, consumer/professional audio, video, and imaging, and ultra-precision data acquisition. cirrus logics manufacturing strategy ensures maximum product quality and availability, as well as access to world-class processing technologies through joint ventures with ibm a and lucent technologies a . contact one of our systems and applications specialists to see how your company can bene?t from the high value cirrus logic adds to its customers products. copyright ? 1998 cirrus logic, inc. all rights reserved. advance product information describes products that are in development and subject to developmental changes. cirrus logic, inc. has ma de best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to chan ge without notice. no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other righ ts of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, or trade secrets. no part of this publi cation may be copied, reproduced, stored in a retrieval system or transmitted in any form or by any means (electronic, mechanical, photographic, or otherwise) or used as the basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. cirrus, cirrus logic, accupak, alpine , clear3d, crystal, crystalclear, crystalclear imaging, crystalware, directvpm, diva, fasten, fastpath, featurechips, filterjet, get into it, good data, intellifilter, laguna, laguna3d, lagunatv, matterhorn, matterhorn3d, mediadac, mediamax, mergent, mojave, motionvideo, multimedia in the mix, mva, sim ulscan, s/la, smartanalog, smash, softarget, soundfusion, stargate, systems in silicon, texturejet, true-d, tvtap, uxart, visualmedia, vpm, v -port, v-port manager, voyager, waveport, and webset are trademarks of cirrus logic, inc., which may be registered in some jurisdictions. othe r trademarks in this document belong to their respective companies. crus and cirrus logic international, ltd. are trade names of cirrus logic, inc. domestic n. california fremont tel: 510/623-8300 fax: 510/252-6020 s. california westlake village tel: 805/371-5860 fax: 805/371-5861 northwestern area portland, or tel: 503/620-5547 fax: 503/620-5665 south central area austin, tx tel: 512/255-0080 fax: 512/255-0733 houston, tx tel: 281/257-2525 fax: 281/257-2555 northeastern area andover, ma tel: 978/794-9992 fax: 978/794-9998 southeastern area raleigh, nc tel: 919/859-5210 fax: 919/859-5334 boca raton, fl tel: 561/395-1613 fax: 561/395-1373 international china beijing tel: 86/10-6428-0783 fax: 86/10-6428-0786 france paris tel: 33/1-48-12-2812 fax: 33/1-48-12-2810 germany herrsching tel: 49/81-52-92460 fax: 49/81-52-924699 hong kong tsimshatsui tel: 852/2376-0801 fax: 852/2375-1202 italy milan tel: 39/2-3360-5458 fax: 39/2-3360-5426 japan tokyo tel: 81/3-3340-9111 fax: 81/3-3340-9120 korea seoul tel: 82/2-565-8561 fax: 82/2-565-8565 singapore tel: 65/743-4111 fax: 65/742-4111 taiwan taipei tel: 886/2-2718-4533 fax: 886/2-2718-4526 united kingdom london, england tel: 44/01628-472211 fax: 44/01628-486114

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